Patents by Inventor Sebastien Kerdiles

Sebastien Kerdiles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8580654
    Abstract: The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: November 12, 2013
    Assignee: Soitec
    Inventors: Sébastien Kerdiles, Daniel Delprat
  • Publication number: 20130295696
    Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions which are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.
    Type: Application
    Filed: July 2, 2013
    Publication date: November 7, 2013
    Inventors: Sébastien Kerdiles, Walter Schwarzenbach, Aziz Alami-Idrissi
  • Publication number: 20130273712
    Abstract: A method for fabricating a silicon-on-insulator structure includes forming a first oxide layer on a silicon donor substrate, forming a second oxide layer on a supporting substrate, and forming a weakened zone in the donor substrate. The donor substrate is bonded to the supporting substrate by establishing direct contact between the first oxide layer on the silicon donor substrate and the second oxide layer on the supporting substrate and establishing a direct oxide-to-oxide bond therebetween. The donor substrate is split along the weakened zone to form a silicon-on-insulator structure, and the silicon-on-insulator structure is subjected to two successive rapid thermal annealing processes at temperatures T1 and T2 respectively, wherein T1 is less than or equal to T2, T1 is between 1200° C. and 1300° C., T2 is between 1240° C. and 1300° C., and when T1 is below 1240° C., then T2 is above 1240° C.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 17, 2013
    Inventors: Carole David, Sébastien Kerdiles
  • Patent number: 8476148
    Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions which are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: July 2, 2013
    Assignee: Soitec
    Inventors: Sébastien Kerdiles, Walter Schwarzenbach, Aziz Alami-Idrissi
  • Patent number: 8461018
    Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: June 11, 2013
    Assignee: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Eric Neyret, Sebastien Kerdiles
  • Patent number: 8435897
    Abstract: A method for reclaiming a surface of a substrate, wherein the surface, in particular a silicon surface, comprises a protruding residual topography, comprising at least the layer of a first material. By providing a filling material in the non-protruding areas of the surface of the substrate and the subsequent polishing, the reclaiming can be carried out such that the material consuming double-sided polishing step used in the prior art is no longer necessary.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: May 7, 2013
    Assignee: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Aziz Alami-Idrissi, Sebastien Kerdiles, Walter Schwarzenbach
  • Patent number: 8420500
    Abstract: The invention relates to a method of producing a semiconductor structure by transferring a layer of a donor substrate to a receiver substrate, with the creation of an embrittlement zone in the donor substrate to define the transfer layer, and the treatment of the surface of one of the substrates to increase the bonding strength between them, followed by the direct wafer bonding of the substrates and the detachment of the donor substrate at the embrittlement zone to form the semiconductor structure, in which the surface of the receiver substrate, except for a peripheral crown, is covered with the transferred layer. The treatment of the substrate surface is controlled so that the bonding strength between the substrates is lower in a peripheral area than in a central area. The peripheral area has a width at least equal to the that of the crown and less than 10 mm.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: April 16, 2013
    Assignee: Soitec
    Inventors: Brigitte Soulier-Bouchet, Sébastien Kerdiles, Walter Schwarzenbach
  • Patent number: 8389412
    Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: March 5, 2013
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Sébastien Kerdiles, Patrick Reynaud, Ludovic Ecarnot, Eric Neyret
  • Patent number: 8357587
    Abstract: The invention relates to a method for routing a chamfered substrate, having applications in the field of electronics, optics, or optoelectronics, which involves depositing a layer of a protective material on a peripheral annular zone of the substrate preferably with the aid of a plasma, partially etching the protective material with the aid of a plasma, so as to preserve a protective ring of the deposited material on the front face of the substrate, this ring located at a distance from the edge of the substrate, so as to delimit an accessible peripheral annular zone, etching a thickness of the material constituting the substrate to be routed, preferably with the aid of a plasma that is level with the accessible peripheral annular zone of the substrate, and removing the ring of protective material preferably with the aid of a plasma.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: January 22, 2013
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Aziz Alami-Idrissi, Alexandre Chibko, Sébastien Kerdiles
  • Patent number: 8349703
    Abstract: The invention relates to a method of forming a structure comprising a thin layer of semiconductor material transferred from a donor substrate onto a second substrate, wherein two different atomic species are co-implanted under certain conditions into the donor substrate so as to create a weakened zone delimiting the thin layer to be transferred. The two different atomic species are implanted so that their peaks have an offset of less than 200 ? in the donor substrate, and the substrates are bonded together after roughening at least one of the bonding surfaces.
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: January 8, 2013
    Assignee: Soitec
    Inventors: Sébastien Kerdiles, Willy Michel, Walter Schwarzenbach, Daniel Delprat, Nadia Ben Mohamed
  • Publication number: 20130005122
    Abstract: The invention relates to finishing a substrate of the semiconductor-on-insulator (SeOI) type comprising an insulator layer buried between two semiconducting material layers. The method successively comprises: routing the annular periphery of the substrate so as to obtain a routed substrate, and encapsulating the routed substrate so as to cover the routed side edge of the buried insulator layer by means of a semiconducting material.
    Type: Application
    Filed: March 14, 2011
    Publication date: January 3, 2013
    Applicant: SOITEC
    Inventors: Walter Schwarzenbach, Aziz Alami-Idrissi, Alexandre Chibko, Sebastien Kerdiles
  • Publication number: 20120319121
    Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 20, 2012
    Applicant: SOITEC
    Inventors: Patrick Reynaud, Sébastien Kerdiles, Daniel Delprat
  • Publication number: 20120223419
    Abstract: A method for controlling the distribution of the stresses in a structure of the semiconductor-on-insulator type during its manufacturing, which includes a thin layer of semiconducting material on a supporting substrate and an insulating layer present on each of the front and rear faces of the supporting substrate, with the insulating layer on the front face forming at least one portion of a thick buried insulator (BOX) layer. The method includes the adhesive bonding of the thin layer onto the supporting substrate. Prior to this adhesive bonding, the insulating layer on the rear face of the supporting substrate is covered with a distinct material that is capable of withstanding deoxidation. The covering material, in combination with this insulating layer on the rear face of the supporting substrate, at least partly compensates for the stress exerted by the buried insulator (BOX) on the supporting substrate.
    Type: Application
    Filed: April 27, 2012
    Publication date: September 6, 2012
    Applicant: SOITEC
    Inventors: Sébastien Kerdiles, Patrick Reynaud
  • Patent number: 8216916
    Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: July 10, 2012
    Assignee: S.O.I. TEC Silicon on Insulator Technologies
    Inventors: Eric Neyret, Sebastien Kerdiles
  • Patent number: 8183128
    Abstract: A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate, and then smoothing the exposed rough surface of the insulator layer by exposure to a gas plasma in a chamber. The chamber contains therein a gas at a pressure of greater than 0.25 Pa but less than 30 Pa, and the gas plasma is created using a radiofrequency generator applying to the insulator layer a power density greater than 0.6 W/cm2 but less than 10 W/cm2 for at least 10 seconds to less than 200 seconds. Substrate bonding and layer transfer may be carried out subsequently to transfer the thin layer of substrate and the insulator layer to a second substrate.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: May 22, 2012
    Assignee: Soitec
    Inventors: Nicolas Daval, Sebastien Kerdiles, Cécile Aulnette
  • Patent number: 8158013
    Abstract: The invention relates to a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: April 17, 2012
    Assignee: Soitec
    Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
  • Publication number: 20120088350
    Abstract: The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 12, 2012
    Inventors: Sébastien Kerdiles, Daniel Delprat
  • Patent number: 8153504
    Abstract: The invention relates to a process for manufacturing a composite substrate comprising bonding a first substrate onto a second semiconducting substrate, characterized in that the process includes, before bonding, the formation of a bonding layer between the first and the second substrate, the bonding layer comprising a plurality of islands distributed over a surface of the first substrate in a determined pattern and separated from one another by regions of a different type, which are distributed in a complementary pattern, wherein the islands are formed via a plasma treatment of the material of the first substrate.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: April 10, 2012
    Assignee: Soitec
    Inventors: Frederic Allibert, Sebastien Kerdiles
  • Publication number: 20120021613
    Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.
    Type: Application
    Filed: March 17, 2010
    Publication date: January 26, 2012
    Inventors: Walter Schwarzenbach, Sébastien Kerdiles, Patrick Reynaud, Ludovic Ecarnot, Eric Neyret
  • Patent number: 8091601
    Abstract: The invention relates to equipment for carrying out a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral