Patents by Inventor Sebastien Marineau-Mes

Sebastien Marineau-Mes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060206887
    Abstract: An adaptive partition scheduler is a priority-based scheduler that also provides execution time guarantees (fair-share). Execution time guarantees apply to threads or groups of threads when the system is overloaded. When the system is not overloaded, threads are scheduled based strictly on priority, maintaining strict real-time behavior. Even when overloaded, the scheduler provides real-time guarantees to a set of critical threads, as specified by the system architect.
    Type: Application
    Filed: August 31, 2005
    Publication date: September 14, 2006
    Inventors: Dan Dodge, Attila Danko, Sebastien Marineau-Mes, Peter Veen, Colin Burgess, Thomas Fletcher, Brian Stecher
  • Publication number: 20060206881
    Abstract: A system is set forth that includes a processor, one or more memory storage units, and software code stored in the one or more memory storage units. The software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with one or more process threads. Each of the plurality of adaptive partitions has a corresponding processor time budget. One or more of the process threads are designated as critical threads. Each adaptive partition associated with a critical thread is assigned a corresponding critical time budget. The software code also includes a scheduling system that is executable by the processor for selectively allocating the processor to run the process threads based, at least in part, on the processor time budgets of the respective adaptive partitions.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 14, 2006
    Inventors: Dan Dodge, Attilla Danko, Sebastien Marineau-Mes, Peter van der Veen, Colin Burgess, Thomas Fletcher, Brian Stecher
  • Publication number: 20060182137
    Abstract: An asynchronous message passing mechanism that allows for multiple messages to be batched for delivery between processes, while allowing for full memory protection during data transfers and a lockless mechanism for speeding up queue operation and queuing and delivering messages simultaneously.
    Type: Application
    Filed: June 3, 2005
    Publication date: August 17, 2006
    Inventors: Hao Zhou, Sebastien Marineau-Mes, Peter van der Veen, Pardeep Kathail, Steve Belair
  • Patent number: 6981244
    Abstract: An operating system architecture and method which provides for transparent inheritance of memory management policies in data processing systems and enhanced memory management is disclosed. The operating system provides for a special “debug” process flag to be associated with debug and device management processes. When a source process transmits a message to a destination process, the operating system determines whether the source process is a debug process (i.e., whether the source process contains a debug process flag indicator associated therewith). If the source process is a debug process, a debug process flag indicator is also associated with the destination process. The operating system also reserves a portion of the device's memory (a reserve memory pool) which is only allocated to special “debug” process when the non-reserved pool of memory is depleted.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: December 27, 2005
    Assignee: Cisco Technology, Inc.
    Inventors: Pradeep K. Kathail, Haresh Kheskani, Srinivas Podila, Sebastien Marineau-Mes