Abstract: An example power semiconductor device includes a silicon carbide semiconductor structure. The example power semiconductor device includes at least one heterodoped layer in the silicon carbide semiconductor structure. In some implementations, the heterodoped layer includes a first layer having a first dopant concentration of a first conductivity type in a range of about 1×1017/cm3 to about 2×1021/cm3. The heterodoped layer includes a second layer having a second dopant concentration of the first conductivity type that is less than the first dopant concentration of the first layer. In some examples, the second layer may be undoped.

Abstract: An example power semiconductor device includes a silicon carbide semiconductor structure. The example power semiconductor device includes at least one heterodoped layer in the silicon carbide semiconductor structure. In some implementations, the heterodoped layer includes a first layer having a first dopant concentration of a first conductivity type in a range of about 1×1017/cm3 to about 2×1021/cm3. The heterodoped layer includes a second layer having a second dopant concentration of the first conductivity type that is less than the first dopant concentration of the first layer. The semiconductor structure includes a drift region, wherein the drift region has a third dopant concentration of the first conductivity type. The third dopant concentration is less than the first dopant concentration.

Abstract: A wide band-gap semiconductor layer structure is provided that comprises a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches are provided in an upper surface of the wide band-gap semiconductor layer structure. Second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure to simultaneously form well regions underneath the source regions and trench shielding regions underneath the trenches, the well regions and the trench shielding regions each having a second conductivity type.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a gate trench formed in an upper surface thereof, a gate finger in the gate trench, a supplemental dielectric layer on an upper surface of the gate finger and vertically overlaps the gate trench, and a gate connector on an upper surface of the supplemental dielectric layer and on an upper surface of the gate finger.

Abstract: A semiconductor device comprises a semiconductor layer structure comprising a drift region having a first conductivity type, a first gate electrode on the semiconductor layer structure that extends along a first longitudinal axis, a second gate electrode on the semiconductor layer structure that extends along a second longitudinal axis, and a first ohmic line that extends continuously in the semiconductor layer structure along a first transverse axis. The first and second longitudinal axes cross the first transverse axis when the semiconductor device is viewed from above.

Abstract: A semiconductor device comprises a semiconductor layer structure comprising a drift region having a first conductivity type, a first gate electrode on the semiconductor layer structure that extends along a first longitudinal axis, a second gate electrode on the semiconductor layer structure that extends along a second longitudinal axis, and a first ohmic line that extends continuously in the semiconductor layer structure along a first transverse axis. The first and second longitudinal axes cross the first transverse axis when the semiconductor device is viewed from above.

Abstract: A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.

Abstract: A vertical semiconductor device includes a drift layer, a mesa on the drift layer, and a trench adjacent to the mesa. The mesa includes a mesa sidewall, a channel layer and a source layer on the channel layer. The channel layer is between the source layer and the drift layer. A sidewall gate region in the mesa adjacent the mesa sidewall and a sidewall channel region is in the channel layer adjacent the sidewall gate region. The channel layer is doped with first conductivity type dopants and has a first doping concentration. The sidewall channel region is doped with first conductivity type dopants and has a second doping concentration that is greater than the first doping concentration. The sidewall gate region extends deeper toward the drift layer than the sidewall channel region.

Abstract: A power semiconductor device includes a semiconductor structure having a first side, a second side, and a drift region of a first conductivity type therebetween, and implanted regions of a second conductivity type in the semiconductor structure adjacent the first side of the semiconductor structure. The implanted regions include first portions of a first material and second portions of a second material, with the second portions positioned between the first portions and the second side. The second material has an atomic weight that is lighter than that of the first material. Related fabrication methods are also discussed.

Abstract: A vertical junction field effect (JFET) semiconductor device according to some embodiments includes a drift layer, a channel layer on the drift layer, and a plurality of alternating trenches and mesas in the channel layer, wherein a first plurality of the trenches includes gate contact regions. A source metallization is on the mesas. The device includes a second different than the first plurality of trenches, wherein the source metallization is electrically connected to the drift layer at a bottom of the second trench.

Abstract: A silicon carbide semiconductor device includes a drift layer, a channel layer on the drift layer, the channel layer having a first conductivity type, a trench in the channel layer and a mesa adjacent to the trench, and a gate region within the trench. The gate region has a second conductivity type opposite the first conductivity type, and the gate region includes an epitaxially regrown layer. A method of forming a silicon carbide semiconductor device includes providing a drift layer, forming a channel layer on the drift layer, the channel layer having a first conductivity type, etching the channel layer to form a trench in the channel layer and a mesa adjacent to the trench, and epitaxially regrowing a gate region within the trench, wherein the gate region has a second conductivity type opposite the first conductivity type.

Abstract: Semiconductor devices are provided that comprise a semiconductor layer structure that comprises a drift region having a first conductivity type and a gate junction region having a second conductivity type, and a gate trench in the semiconductor layer structure. At least a portion of the gate junction region that is on a sidewall of the gate trench may have a tapered shape in a cross-sectional view.

Abstract: A semiconductor device comprises a semiconductor layer structure that comprises a drift layer having a first conductivity type, a first well region having a second conductivity type, a second well region having the second conductivity type and a JFET region having the first conductivity type, where the JFET region has a doping concentration that is higher than a doping concentration of the drift layer. A gate trench is provided in the semiconductor layer structure. The first well region forms a first sidewall of the gate trench and the second well region forms a second sidewall of the gate trench. Additionally, first and second sidewalls of the JFET region are aligned with respective first and second sidewalls of the gate trench.

Abstract: A gate-controlled semiconductor device comprises a semiconductor layer structure and a gate trench in the semiconductor layer structure. The semiconductor layer structure comprises a drift region that has a first conductivity type, a trench shield that has a second conductivity type underneath the gate trench, and a support shield that has the second conductivity type extending toward a lower surface of the semiconductor layer structure. The support shield has a peak doping concentration at a first depth from the upper surface of the semiconductor layer structure. A lowermost portion of the trench shield is at a second depth from the upper surface of the semiconductor layer structure that is less than the first depth, and a thickness of the trench shield is less than the first depth minus the second depth.

Abstract: A gate-controlled semiconductor device comprises a semiconductor layer structure and a gate trench in the semiconductor layer structure. The semiconductor layer structure comprises a drift region that has a first conductivity type, a trench shield that has a second conductivity type underneath the gate trench, and a support shield that has the second conductivity type extending toward a lower surface of the semiconductor layer structure. The support shield has a peak doping concentration at a first depth from the upper surface of the semiconductor layer structure. A lowermost portion of the trench shield is at a second depth from the upper surface of the semiconductor layer structure that is less than the first depth, and a thickness of the trench shield is less than the first depth minus the second depth.

Abstract: A semiconductor device includes a drift layer including silicon carbide and having a first conductivity type, a channel layer on the drift layer, the channel layer including silicon carbide and having the first conductivity type, and a source layer on the channel layer, the source layer including silicon carbide and having the first conductivity type. The device includes first and second trenches extending through the source layer and at least partially into the channel layer. The first and second trenches define a mesa therebetween having a mesa sidewall adjacent the channel layer. A heterojunction layer is in the first trench. The heterojunction layer includes a semiconductor material having a second conductivity type opposite the first conductivity type, wherein the heterojunction layer forms a PN heterojunction with silicon carbide.

Abstract: A semiconductor device includes semiconductor layer, a gate pad on the semiconductor layer, and a longitudinal gate finger on the semiconductor layer, the longitudinal gate finger having opposing first and second ends. The semiconductor device includes a first gate bus segment on the semiconductor layer. The first gate bus segment extends adjacent the first end of the longitudinal gate finger and has a proximal end nearest the gate pad and a distal end farthest from the gate pad. The first gate bus segment has a first width at the proximal end and a second width at the distal end. The first width is greater than the second width.

Abstract: JFETs are provided that comprise a wide bandgap semiconductor layer structure comprising an active region and a termination region. The termination region comprises a plurality of termination structures. A first major surface of the semiconductor layer structure in the active region comprises a plurality of spaced-apart mesas and the first major surface of the semiconductor layer structure in the termination region is a planar surface.

Abstract: A semiconductor device includes an active region comprising first and second mesa stripes and a trench between the mesa stripes. The trench has a first width between the first and second mesa stripes near a central portion of the first and second mesa stripes and a second width between the first and second mesa stripes near end portions of the first and second mesa stripes. The second width is less than the first width.

Abstract: A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.