Patents by Inventor Sei-Hyung Ryu

Sei-Hyung Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387620
    Abstract: A semiconductor device includes a semiconductor layer having a first conductivity type, a well region in the semiconductor layer, the well region having a second conductivity type opposite the first conductivity type, a source region having the first conductivity type in the well region, and an implanted charge compensation region in the semiconductor layer beneath the well region. The source region is adjacent a channel region in the well region. A method of forming a semiconductor device includes forming a well region having a second conductivity type in a semiconductor layer having a first conductivity type opposite the second conductivity type, forming a source region having the first conductivity type in the well region, and implanting ions into the semiconductor layer to form a charge compensation region in the semiconductor layer beneath the well region. The source region is adjacent a channel region in the well region.
    Type: Application
    Filed: March 7, 2024
    Publication date: November 21, 2024
    Inventors: Kijeong Han, Jeff Kim, Sei-Hyung Ryu, Daniel Lichtenwalner
  • Publication number: 20240379667
    Abstract: Shielding techniques are used to provide an embedded sensor element such as a temperature sensing element on a wide bandgap power semiconductor device. A semiconductor device may include a drift layer and an embedded sensor element. The drift layer may be a wide bandgap semiconductor material. A shielding structure is provided in the drift layer below the embedded sensor element. The embedded sensor element may be provided between contacts that are in electrical contact with the shielding well. The distance between the contacts may be minimized. A noise reduction well may be provided between the contacts to further isolate the embedded sensor element from parasitic signals.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Joohyung Kim, Sei-Hyung Ryu, Kijeong Han, Thomas E. Harrington, III, Edward Robert Van Brunt
  • Patent number: 12094926
    Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a deep shielding pattern that may improve a reliability and/or a functioning of the device. An example method may include forming a wide band-gap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region that has a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches spaced apart from each other, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; forming an obstruction over a portion of each gate trench that partially obscures the upper opening; and implanting dopants having a second conductivity type that is opposite the first conductivity type into the bottom surfaces of the gate trenches, where the dopants implanted into the bottom surface of the gate trenches form deep shielding patterns.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: September 17, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Daniel J. Lichtenwalner, Naeem Islam, Woongsun Kim, Sei-Hyung Ryu
  • Patent number: 12087854
    Abstract: A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: September 10, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Daniel Jenner Lichtenwalner, Sei-Hyung Ryu, Kijeong Han, Edward Robert Van Brunt
  • Patent number: 12080790
    Abstract: A power semiconductor device comprises a semiconductor layer structure comprising a drift region that comprises a wide band-gap semiconductor material that has a first conductivity type, a well region that has a second conductivity type, and a source region that has the first conductivity type in an upper portion of the well region and a gate trench in an upper portion of the semiconductor layer structure and comprising a portion obliquely angled in plan view. Sidewalls of the gate trench may extend along substantially the same crystal plane in the semiconductor layer structure.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: September 3, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Woongsun Kim, Daniel Jenner Lichtenwalner, Sei-Hyung Ryu, Naeem Islam
  • Publication number: 20240290832
    Abstract: A power semiconductor device includes semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type. The guard rings extend into a surface of the semiconductor drift region. The guard rings respectively comprise a first portion adjacent the surface and a second portion spaced from the surface, where the first portion is wider than the second portion. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: May 10, 2024
    Publication date: August 29, 2024
    Inventors: Woongsun Kim, Daniel Jenner Lichtenwalner, Sei-Hyung Ryu, Naeem Islam
  • Patent number: 12074079
    Abstract: Shielding techniques are used to provide an embedded sensor element such as a temperature sensing element on a wide bandgap power semiconductor device. A semiconductor device may include a drift layer and an embedded sensor element. The drift layer may be a wide bandgap semiconductor material. A shielding structure is provided in the drift layer below the embedded sensor element. The embedded sensor element may be provided between contacts that are in electrical contact with the shielding well. The distance between the contacts may be minimized. A noise reduction well may be provided between the contacts to further isolate the embedded sensor element from parasitic signals.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: August 27, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Joohyung Kim, Sei-Hyung Ryu, Kijeong Han, Thomas E. Harrington, III, Edward Robert Van Brunt
  • Publication number: 20240266432
    Abstract: A semiconductor device includes a vertical transistor and a body diode. Various improvements to the semiconductor device allow for improved performance of the body diode, in particular to reduced snappiness and increased softness.
    Type: Application
    Filed: April 16, 2024
    Publication date: August 8, 2024
    Inventors: Kijeong Han, Sei-Hyung Ryu, Daniel Jenner Lichtenwalner
  • Publication number: 20240234495
    Abstract: A method of forming a semiconductor device comprises forming a first mask that includes a longitudinally-extending first opening that has a first width on a semiconductor layer structure. A spacer is formed on sidewalls of the first mask that are exposed by the first opening to form a second mask, where the first and second masks comprise a mask structure that has a longitudinally-extending second opening that has a second width that is smaller than the first width. Dopants are implanted through the second opening to form an implanted region in the semiconductor layer structure. The spacer is at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure underneath the third opening.
    Type: Application
    Filed: January 5, 2023
    Publication date: July 11, 2024
    Inventors: Woongsun Kim, Naeem Islam, Madankumar Sampath, Sei-Hyung Ryu, Rahul R. Potera, In-Hwan Ji
  • Publication number: 20240234507
    Abstract: A semiconductor device includes a semiconductor layer structure having a drift region of a first conductivity type and a well region of a second conductivity type above the drift region. A gate is provided on the semiconductor layer structure adjacent the well region. A buried shielding structure of the second conductivity type is provided under the well region and separated from the well region by a portion of the drift region. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: January 5, 2023
    Publication date: July 11, 2024
    Inventors: Madankumar Sampath, Sei-Hyung Ryu, Daniel Jenner Lichtenwalner, Woongsun Kim, Naeem Islam
  • Publication number: 20240234567
    Abstract: A semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type above the drift region, a gate on the semiconductor layer structure adjacent the well region, and a contact shielding structure of the second conductivity type that vertically extends from the well region into the drift region, and discontinuously extends in one or more lateral directions. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: September 22, 2023
    Publication date: July 11, 2024
    Inventors: Madankumar Sampath, Naeem Islam, Woongsun Kim, Sei-Hyung Ryu
  • Patent number: 12009389
    Abstract: A power semiconductor device includes semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type. The guard rings extend into a surface of the semiconductor drift region. The guard rings respectively comprise a first portion adjacent the surface and a second portion spaced from the surface, where the first portion is wider than the second portion. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: June 11, 2024
    Assignee: WOLFSPEED, INC.
    Inventors: Woongsun Kim, Daniel Jenner Lichtenwalner, Sei-Hyung Ryu, Naeem Islam
  • Publication number: 20240178314
    Abstract: A vertical semiconductor device includes a substrate, a drift region over the substrate, an upper region on the drift region, a top surface over the upper region and being substantially planar, and a series of implants of a second dopant in the upper region, such that each implant of the series of implants is located at a different depth below the top surface. The series of implants forms at least two gate region. The substrate and the drift region are doped with a first dopant of a first polarity. The second dopant has a second polarity opposite that of the first polarity. At least a portion of a channel region is provided between the at least two gate regions, and a conducting gap is defined within the channel region and between opposing sidewalls of the at least two gate regions.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 30, 2024
    Inventors: Daniel Jenner Lichtenwalner, Sei-Hyung Ryu, Arman Ur Rashid
  • Patent number: 11990543
    Abstract: A semiconductor device includes a vertical transistor and a body diode. Various improvements to the semiconductor device allow for improved performance of the body diode, in particular to reduced snappiness and increased softness.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: May 21, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Kijeong Han, Sei-Hyung Ryu, Daniel Jenner Lichtenwalner
  • Patent number: 11894455
    Abstract: A precursor for a vertical semiconductor device is provided with a substrate, a drift region over the substrate, and an upper precursor region over the drift region. The top surface of the precursor is substantially planar, and the substrate and the drift region are doped with a first dopant of a first polarity. In a first embodiment, a series of implants with a second dopant is provided in the upper precursor region via the top surface to form each of at least two gate regions such that each implant of the series of implants is provided at a different depth below the top surface. In a second embodiment, a series of implants with the first dopant is provided in the upper precursor region via the top surface to form a channel region that has at least a portion between two gate regions.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: February 6, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Daniel Jenner Lichtenwalner, Sei-Hyung Ryu, Arman Ur Rashid
  • Publication number: 20230420536
    Abstract: A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Inventors: Madankumar Sampath, Sei-Hyung Ryu, Rahul R. Potera
  • Publication number: 20230420527
    Abstract: A semiconductor device includes a semiconductor layer structure comprising a gate trench formed in an upper surface thereof, a gate finger in the gate trench, a supplemental dielectric layer on an upper surface of the gate finger and vertically overlaps the gate trench, and a gate connector on an upper surface of the supplemental dielectric layer and on an upper surface of the gate finger.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Inventors: Madankumar Sampath, Woongsun Kim, Naeem Islam, Sei-Hyung Ryu
  • Publication number: 20230411446
    Abstract: A wide band-gap semiconductor layer structure is provided that comprises a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches are provided in an upper surface of the wide band-gap semiconductor layer structure. Second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure to simultaneously form well regions underneath the source regions and trench shielding regions underneath the trenches, the well regions and the trench shielding regions each having a second conductivity type.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Inventors: Madankumar Sampath, Sei-Hyung Ryu, Naeem Islam, Woongsun Kim
  • Patent number: 11843061
    Abstract: A power semiconductor device has a semiconductor layer structure that includes a silicon carbide drift region having a first conductivity type, first and second wells in the silicon carbide drift region that are doped with dopants having a second conductivity type, and a JFET region between the first and second wells. The first and second wells each include a main well and a side well that is between the main well and the JFET region, and each side well includes a respective channel region. A doping concentration of the JFET region exceeds a doping concentration of the silicon carbide drift region, and a minimum width of an upper portion of the JFET region is greater than a minimum width of a lower portion of the JFET region.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: December 12, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Kijeong Han, Joohyung Kim, Sei-Hyung Ryu
  • Patent number: 11837657
    Abstract: A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: December 5, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Naeem Islam, Woongsun Kim, Daniel J. Lichtenwalner, Sei-Hyung Ryu