Abstract: Power semiconductor devices include a semiconductor layer structure comprising an active area with a plurality of unit cell transistors and an inactive gate pad area, a gate resistor layer on an upper side of the semiconductor layer structure, an inner contact that is directly on the upper side of the gate resistor layer, and an outer contact that is directly on the upper side of the gate resistor layer. The outer contact encloses the inner contact within the inactive gate pad area of the semiconductor device.

Abstract: A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench.

Abstract: Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.

Abstract: A precursor for a vertical semiconductor device is provided with a substrate, a drift region over the substrate, and an upper precursor region over the drift region. The top surface of the precursor is substantially planar, and the substrate and the drift region are doped with a first dopant of a first polarity. In a first embodiment, a series of implants with a second dopant is provided in the upper precursor region via the top surface to form each of at least two gate regions such that each implant of the series of implants is provided at a different depth below the top surface. In a second embodiment, a series of implants with the first dopant is provided in the upper precursor region via the top surface to form a channel region that has at least a portion between two gate regions.

Abstract: A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction.

Abstract: Power semiconductor devices comprise a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, a plurality of gate fingers on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors electrically coupled between the gate pad and the gate fingers.

Abstract: A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.

Abstract: A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.

Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Abstract: Power semiconductor devices include a semiconductor layer structure comprising an active area with a plurality of unit cell transistors and an inactive gate pad area, a gate resistor layer on an upper side of the semiconductor layer structure, an inner contact that is directly on the upper side of the gate resistor layer, and an outer contact that is directly on the upper side of the gate resistor layer. The outer contact encloses the inner contact within the inactive gate pad area of the semiconductor device.

Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a wide bandgap semiconductor material. The semiconductor layer structure includes a drift region of a first conductivity type and a plurality of fin structures protruding from the drift region. The fin structures comprise respective source regions of the first conductivity type and respective channel regions between the respective source regions and the drift region. Related devices and methods are also discussed.

Abstract: A transistor includes a substrate, a drift layer on the substrate, and a junction implant in the drift layer opposite the substrate. The junction implant includes a body well and a source well within the body well. A source contact is in electrical contact with the source well and the body well. A drain contact is in electrical contact with the substrate. A gate insulator is on the drift layer and over a portion of the body well and the source well. A gate contact is on the gate insulator. A softness of a body diode between the source contact and the drain contact is greater than 0.5. By providing the transistor such that the softness factor of the body diode is greater than 0.5, the switching performance of the body diode and thus switching losses of the transistor when used in a bidirectional conduction application will be significantly reduced.

Abstract: A semiconductor device includes a vertical transistor and a body diode. Various improvements to the semiconductor device allow for improved performance of the body diode, in particular to reduced snappiness and increased softness.

Abstract: A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench.

Abstract: Power switching devices include a semiconductor layer structure, a unit cell transistor comprising a gate finger, the gate finger extending in a first direction in a gate trench that is below a surface of the semiconductor layer structure, and a gate bus, wherein a portion of the gate bus vertically overlaps the gate finger and is electrically connected to the gate finger.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, a plurality of gate trenches including respective gate insulating layers and gate electrodes therein extending into the drift region, respective shielding patterns of the second conductivity type in respective portions of the drift region adjacent the gate trenches, and respective conduction enhancing regions of the first conductivity type in the respective portions of the drift region. The drift region comprises a first concentration of dopants of the first conductivity type, and the respective conduction enhancing regions comprise a second concentration of the dopants of the first conductivity type that is higher than the first concentration. Related devices and fabrication methods are also discussed.

Abstract: Semiconductor devices, and in particular protection structures for semiconductor devices that include sensor arrangements are disclosed. A semiconductor device may include a sensor region, for example a current sensor region that occupies a portion of an overall active area of the device. The current sensor region may be configured to provide monitoring of device load currents during operation. Semiconductor devices according to the present disclosure include one or more protection structures that are configured to allow the semiconductor devices to withstand transient voltage events without device failure. A protection structure may include an insulating layer that is provided in a transition region between a device region and the sensor region of the semiconductor device. In the example of an insulated gate semiconductor device, the insulating layer of the protection structure may include a material with a greater breakdown voltage than a breakdown voltage of a gate insulating layer.

Abstract: Semiconductor devices, and more particularly passivation structures for semiconductor devices are disclosed. A semiconductor device may include an active region, an edge termination region that is arranged along a perimeter of the active region, and a passivation structure that may form a die seal along the edge termination region. The passivation structure may include a number of passivation layers in an arrangement that improves mechanical strength and adhesion of the passivation structure along the edge termination region. An interface formed by at least one of the passivation layers may be provided with a pattern that serves to more evenly distribute forces related to thermal expansion and contraction during power cycling, thereby reducing cracking and delamination in the passivation structure. A patterned layer may be at least partially embedded in the passivation structure in an arrangement that forms the corresponding pattern in overlying portions of the passivation structure.

Abstract: Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.