Abstract: A signal synthesizer apparatus having a parameter dependent multiplier which includes charge-coupled devices. The multiplier has a gating input to store a charge corresponding to an input signal applied thereto; a first set of transmission gates for selectively transferring portions of the stored input charge, the selectivity of the transmission gates being dependent on a prescribed parameter; a plurality of intermediate electrodes for storing the charges transferred by the transmission gates; a second set of transmission gates for transferring the charges stored by the intermediate electrodes; and an output electrode for combining all of the charges transferred from the intermediate electrodes by the second set of transmission gates. The signal output by the multiplier corresponds to the magnitude of the combined charges of the output electrode.

Abstract: A multi-processor system includes a plurality of processors, a common shared memory, and programmable memory access priority control circuit. The programmable memory access priority control circuits includes a programmable register circuit and a priority control circuit. The programmable register circuit stores priority information designating a memory access grade priority for each of the processors, wherein the priority information is changeable either manually, by external circuit or by at least one of the processors and remains fixed irrespective of access of the memory by any of the processors until being changed. The register circuit outputs priority information signals which indicate the memory access grade priority of each of the processors. The priority control circuit receives the priority information signals from the register means, receives a memory request signal from the processors requesting memory access (i.e.

Abstract: A multi-processor system having a priority control wherein jobs are transferred between processors in a multi-processor system when a new job is accepted by the system. The processors are arranged in a predetermined priority sequence and in response to an interrupt command, the system always directs a transferred job to which priority processor whose currently executing job is transferred to a lower priority processor. Jobs are transferred by shifting linkage information from one processor to the other through a common control memory in accordance with a job transfer program at each processor. When the interrupt cycle is completed, transferred jobs are returned to the processor at which they were being processed prior to the interrupt.

Abstract: An operand fetch control system wherein an address modification mode code is provided in the instruction word and designates both the general storage location of an operand to be fetched and the mode of addressing required for fetching it. The address modification mode code is a two-bit binary number designating either a direct register addressing mode or a main memory indirect, index, or indirect index addressing mode. Mode code 00 designates the register mode while the codes 10, 01 and 11 designate the indirect mode, the index mode and the indirect index mode, respectively.

Abstract: A multi-processor system wherein a plurality of priority-designated central processor units (CPUs) are interconnected by a program control memory which operates to transfer control (linkage) information between CPUs in response to interrupt commands to enable the total processing capacity of the system to be allocated to the highest priority jobs. Each processor unit employs a job swapping control program which responds to an interrupt command from an external source or from a higher priority unit to cause program status data stored in the CPU to be transferred to the program control memory for holding or for passage to a lower priority CPU. The job swapping program also causes program status data from the higher priority CPU to be transferred from the control memory to the CPU to enable processing of a new job. On completion of the interrupt cycle, the control program effects exchange of status data to restore job assignments to the original CPUs.

Abstract: There are provided a counter, a memory device which stores a combustion delay information, that is an information regarding the time delay between ignition initiation and combustion, and a processor. In response to a clock pulse the counter measures the interval between adjacent combustion initiation points and produces a count information corresponding to the combustion interval. The combustion delay information is read out of the memory device by the count information. The processor produces an ignition time information in response to the count information and the combustion delay information. The ignition time information contains an information corresponding to the difference between the combustion initiation points and the combustion delay time, and is used to generate a succeeding ignition initiation time.

Abstract: The system is constructed to operate to mutually transfer information between a processor and a terminal device via a first-in/first-out type stack. Signal generators are provided on the input and output sides of the stack for generating signals corresponding to the EMPTY and FULL statuses of the stack thereby controlling to inhibit or commence the transfer of the information in response to the direction of transfer of the information and the status of the stack.

Abstract: An interrupt control method for a multiprocessor system including a plurality of microprocessors wherein sections of a main memory, which is shared among the processors of the system, are allocated to store entry address data pointing to a plurality of interrupt-servicing programs for each of the several processors of the system. Interrupt commands are coded to designate different interrupt levels which are compared against mask flag bits and a master mask flag bit unique to each processor to determine which processor will respond to the interrupt command. The processors are arranged in a fixed priority sequence and respond to an interrupt command in a designated priority order. Controls are provided to prevent a processor which is executing an interrupt-servicing program from responding to a subsequent interrupt command until execution of the interrupt-servicing program is completed.

Abstract: A semiconductor memory device comprises a matrix array of a plurality of memory cells wherein a load circuit connected to column lines of the matrix array for charging the column lines is enabled to provide different resistance values between the actions of charging and discharging the column lines.

Abstract: A processor device which comprises a processor unit integrated in a single chip and integrally assembled with a programming system, thereby providing a direct memory access-controlling function for carrying out a direct memory access between a main memory and an input-output device, and a cycle steal-controlling function for selecting a program mode or direct memory access mode.

Abstract: An entry requirement control system in a multiprocessing system having a plurality of central processing units (CPU's), a common main memory for storing a plurality of programs which are accessed by the CPU's, and a key register provided between the CPU's and the common main memory. A flag bit circuit is incorporated into the system in the form of hardware in the key register and is adapted, upon completion of the execution of a program by one CPU, to only give priority to the earliest entry requirement made by a plurality of CPU's to the same program and prohibit the other CPU's from being given any priority. A flag bit circuit corresponding to each program acts, while one program is executed by one CPU, to prohibit an entry requirement from the other CPU's.

Abstract: A data transfer control system for controlling the priority use of a common bus shared by a plurality of data processors which comprises a bus rank memory for storing signals denoting a demand for the priority use of the common bus which are supplied from said plural data processors; and a priority-detecting circuit for detecting the sequential priority positions of signals demanding the priority use of the common bus which are stored in said bus rank memory, wherein the plural data processors are supplied with a control signal instructing the use of the common bus or a waiting position for said use according to the sequential priority positions of the common bus use-demanding signals which have been detected by said priority-detecting circuit.

Abstract: The system comprises a central information processing unit, an input/output unit, a first-in first-out stack which is connected to receive information from the central information processing unit for sending a "FULL" signal to the central information processing unit when the stack is filled with the information sent from the central information processing unit and for sending thereto an "EMPTY" signal when the stack is empty, an input/output control circuit which operates to transfer the information from the first-in first-out stack to the input/output unit and to detect the state thereof for sending a "READY" signal to the central processing unit when the input/output unit is in a state ready for accepting the information, a command register coupled to the central information processing unit to be set at a particular bit by a bit signal sent from the central processing unit when it receives the "FULL" signal from the first-in first-out stack and the "READY" signal from the input/output control circuit, and a

Abstract: The central processing unit (CPU) is interrupted at a predetermined time interval by an external timer. In the CPU, the first priority is given to the interruption and the instruction for refreshing the contents of the dynamic memory or the instruction including such a refreshing function is executed in the intervals of the program execution.

Abstract: A data transfer control system for controlling data transfer between a processor and an input/output device comprises a multi-layer stack for temporarily storing transfer data, such as a first-in first-out stack or a last-in first-out stack; first and second up/down counters having a preset function and permitting any designated address at the stack to be varied; and first and second pointer registers for storing any initially designated address data which is stored in the counter. The first counter permits a direction of a count operation to be determined by the processor and the first point register has an initially designated address data stored therein by the processor. The second counter permits a direction of a count operation to be determined by the input/output device and the second point register has an initially designated address data stored therein by the input/output device.

Abstract: An information transfer control system for controlling the information transfer between a data processor and an input/output device is disposed between the data processor and the input/output device. The information transfer control system comprises a first-in/first-out stack for temporarily storing transferring information being transferred, an up/down counter with a preset function for selectively designating the address lines desired of the stack through a decoder, and a register for setting up a counting range of the counter. The addressing range data to be counted in the up/down counter is initialized in the up/down counter through a program.

Abstract: An information transferring apparatus disposed between first and second information processing units comprises a first-in first-out stack, a first information line for transferring information from the first information processing unit to the first-in first-out stack, a second information line for transferring information from the first-in first-out stack to the second information processing unit, a third information line for transferring information from the second information processing unit to the first-in first-out stack, a fourth information line for transferring information from the first-in first-out stack to the first information processing unit, switching circuits for selectively deactivating the first to fourth information lines, and a command register for applying first and second control signals to the switching circuits, wherein the switching circuits operate responsive to the first control signal from the command register to deactivate the third and fourth information lines while holding active

Abstract: A start and stop control apparatus used in controlling the transmission of a series of data frames each showing a character and each composed of start bit, data and stop bit pulses. The apparatus is so designed as to generate a new sampling pulse for every data frame. A number N of binaries "0" which corresponds to the width of the start bit in each data frame are written into a shift register in response to clock pulses. Upon completion of the writing of binaries "0", the shift register forms a loop. A binary "1" is then written into the shift register in place of the N/2th binary "0" when N is even and N.+-.1th/2 binary "0" when N is odd. Every time the binaries "0" and the binary "1" are circulated in the looped shift register in response to clock pulses, there is obtained from the shift register a sampling pulse by which the data pulses are sampled.

Abstract: A synchronous transmission control system is provided which comprises a first-in/first-out stack storing plural kinds of synchronous pattern signals, a comparator for comparing the synchronous pattern signals with the synchronous pattern signals delivered from a transmitting side, and a controller for switching the data flow in the stack in response to the output of the comparator, in which the comparison of the respective synchronous pattern signals stored in the stack with the synchronous pattern signals delivered from the transmitting side is carried out in the comparator, and, if the comparison shows coincidence between them, the data transmitted from the transmitting side is permitted to enter the receiving side through the stack, with an assumption that synchronization is established between the transmitting and receiving slides, while, if the comparison shows disagreement between them, a synchronous error control is executed.

Abstract: In an information processing system comprising a central processing unit, an input/output unit and a first-in first-out stack connected between these units there are provided a buffer control circuit for detecting the full and empty states of the first-in first-out stack, an input/output control circuit connected between the first-in first-out stack and the input/output unit for detecting a predetermined state of the input/output unit, a status register for storing specific states of the first-in first-out stack and the input/output unit, a command register controlled by programmed information from the central processing unit for establishing a specific interruption condition corresponding to the specific states of the first-in first-out stack and the input/output unit, and an interruption control circuit coupled to the status register and the command register for applying an interruption signal to the central processing unit when the state signal from the status register and the interruption condition signal