Abstract: Precipitation-hardened, martensitic, cast stainless steel having a composition comprising, by mass, 0.08-0.18% of C, 1.5% or less of Si, 2.0% or less of Mn, 0.005-0.4% of S, 13.5-16.5% of Cr, 3.0-5.5% of Ni, 0.5-2.8% of Cu, 1.0-2.0% of Nb, and 0.12% or less of N, the amounts of C, N and Nb meeting the condition of ?0.2?9 (C %+0.86N %)?Nb %?1.0, the rest being Fe and inevitable impurities, and having a structure in which Cu precipitates having an average particle size of 0.1-0.4 ?m are dispersed in a tempered-martensite-based matrix.

Abstract: In the rare earth sintered magnet, the ratio of R2 to the sum of R1 and R2 that are contained in crystal grain boundaries surrounding the crystal grains in the rare earth sintered magnet body is higher than the ratio of R2 to the sum of R1 and R2 in the crystal grains, and the concentration of R2 increases from the central portion of the rare earth sintered magnet body toward the surface of the rare earth sintered magnet body. In addition, the degree of unevenness in residual magnetic flux density on the surface of the rare earth sintered magnet body is smaller than 3.0%.

Abstract: In the rare earth sintered magnet, the ratio of R2 to the sum of R1 and R2 that are contained in crystal grain boundaries surrounding the crystal grains in the rare earth sintered magnet body is higher than the ratio of R2 to the sum of R1 and R2 in the crystal grains, and the concentration of R2 increases from the central portion of the rare earth sintered magnet body toward the surface of the rare earth sintered magnet body. In addition, the degree of unevenness in residual magnetic flux density on the surface of the rare earth sintered magnet body is smaller than 3.0%.

Abstract: Distance ?m between a floating gate and a drain contact of a floating gate transistor forming a memory cell is set to be greater than a distance ? determined based on a minimum design dimension between a control gate and a contact of a peripheral transistor. Data retention characteristics of a programmable memory which stores data in accordance with the amount of accumulated charges in the floating gate can be ensured without being affecting by mask misalignment or the like.

Abstract: A graphite-containing, heat-resistant cast iron for exhaust equipment members used at temperatures exceeding 800° C., comprising 3.5-5.6% of Si and 1.2-15% of W on a weight basis, and having intermediate layers, in which W and Si are concentrated, in the boundaries of graphite particles and a matrix. An exhaust equipment member formed by this heat-resistant cast iron has an AC1 transformation point is 840° C. or higher when measured from 30° C. at a temperature-elevating speed of 3° C./minute, and a thermal cracking life of 780 cycles or more in a thermal fatigue test, in which heating and cooling are conducted under the conditions of an upper-limit temperature of 840° C., a temperature amplitude of 690° C. and a constraint ratio of 0.25.

Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

Abstract: Precipitation-hardened, martensitic, cast stainless steel having a composition comprising, by mass, 0.08-0.18% of C, 1.5% or less of Si, 2.0% or less of Mn, 0.005-0.4% of S, 13.5-16.5% of Cr, 3.0-5.5% of Ni, 0.5-2.8% of Cu, 1.0-2.0% of Nb, and 0.12% or less of N, the amounts of C, N and Nb meeting the condition of ?0.2?9(C %+0.86N %)?Nb %?1.0, the rest being Fe and inevitable impurities, and having a structure in which Cu precipitates having an average particle size of 0.1-0.4 ?m are dispersed in a tempered-martensite-based matrix.

Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

Abstract: A process for production of a magnet which comprises step of supplying a slurry S containing magnetic powder and a dispersing medium into the cavity C of a molding apparatus 12, a step of compression molding the slurry S while applying a magnetic field to the slurry S to obtain a molded article and a step of sintering the molded article to obtain a magnet, wherein the molding apparatus 12 comprises a die 121 having a through-hole 121a into which the slurry S is supplied, a slurry supply gate 121d being formed in the inner wall surface 121b, a die 122 inserted in the through-hole 121a and a die 123 that forms a cavity C together with the dies 123, 122, the slurry S being supplied in an amount such that it is less than the volume of the cavity C when the die 122 has been inserted in the through-hole 121a and has blocked the slurry supply gate 121d, and in the step of obtaining the molded article, the slurry S is compression molded after the die 122 has blocked the slurry supply gate 121d.

Abstract: Distance ?m between a floating gate and a drain contact of a floating gate transistor forming a memory cell is set to be greater than a distance ? determined based on a minimum design dimension between a control gate and a contact of a peripheral transistor. Data retention characteristics of a programmable memory which stores data in accordance with the amount of accumulated charges in the floating gate can be ensured without being affecting by mask misalignment or the like.

Abstract: A process for production of a magnet which comprises step of supplying a slurry S containing magnetic powder and a dispersing medium into the cavity C of a molding apparatus 12, a step of compression molding the slurry S while applying a magnetic field to the slurry S to obtain a molded article and a step of sintering the molded article to obtain a magnet, wherein the molding apparatus 12 comprises a die 121 having a through-hole 121a into which the slurry S is supplied, a slurry supply gate 121d being formed in the inner wall surface 121b, a die 122 inserted in the through-hole 121a and a die 123 that forms a cavity C together with the dies 123, 122, the slurry S being supplied in an amount such that it is less than the volume of the cavity C when the die 122 has been inserted in the through-hole 121a and has blocked the slurry supply gate 121d, and in the step of obtaining the molded article, the slurry S is compression molded after the die 122 has blocked the slurry supply gate 121d.

Abstract: Distance ?m between a floating gate and a drain contact of a floating gate transistor forming a memory cell is set to be greater than a distance ? determined based on a minimum design dimension between a control gate and a contact of a peripheral transistor. Data retention characteristics of a programmable memory which stores data in accordance with the amount of accumulated charges in the floating gate can be ensured without being affecting by mask misalignment or the like.

Abstract: An electrode production method has an active-material-containing layer forming step of applying an electrode-forming coating solution containing an electrode active material, a binder capable of binding the electrode active material, and a liquid capable of dissolving or dispersing the binder, onto a collector sheet, and thereafter removing the liquid to form an active-material-containing layer on the collector, thereby obtaining a electrode sheet; and an electrode forming step of cutting the electrode sheet with a slitter apparatus to obtain an electrode.

Abstract: An integrally cast steel piston for internal engines, the cast steel having (a) a composition comprising 0.8% or less of C, 3% or less of Si, 3% or less of Mn,0.2% or less of S, 3% or less of Ni, 6% or less of Cr, 6% or less of Cu, and 0.01-3% of Nb, the balance being substantially Fe and inevitable impurities, or (b) a composition comprising 0.1-0.8% of C, 3% or less of Si, 3% or less of Mn, 0.2% or less of S, 10% or less of Ni, 30% or less of Cr, 6 % or less of Cu, and 0.05-8% of Nb, the balance being substantially Fe and inevitable impurities, by mass.

Abstract: A graphite-containing, heat-resistant cast iron for exhaust equipment members used at temperatures exceeding 800° C., comprising 3.5-5.6% of Si and 1.2-15% of W on a weight basis, and having intermediate layers, in which W and Si are concentrated, in the boundaries of graphite particles and a matrix. An exhaust equipment member formed by this heat-resistant cast iron has an AC transformation point is 840° C. or higher when measured from 30° C. at a temperature-elevating speed of 3° C./minute, and a thermal cracking life of 780 cycles or more in a thermal fatigue test, in which heating and cooling are conducted under the conditions of an upper-limit temperature of 840° C., a temperature amplitude of 690° C. and a constraint ratio of 0.25.

Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

Abstract: Distance ?m between a floating gate and a drain contact of a floating gate transistor forming a memory cell is set to be greater than a distance ? determined based on a minimum design dimension between a control gate and a contact of a peripheral transistor. Data retention characteristics of a programmable memory which stores data in accordance with the amount of accumulated charges in the floating gate can be ensured without being affecting by mask misalignment or the like.

Abstract: In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

Abstract: An integrally cast steel piston for internal engines, the cast steel having (a) a composition comprising 0.8% or less of C, 3% or less of Si, 3% or less of Mn, 0.2% or less of S, 3% or less of Ni, 6% or less of Cr, 6% or less of Cu, and 0.01-3% of Nb, the balance being substantially Fe and inevitable impurities, or (b) a composition comprising 0.1-0.8% of C, 3% or less of Si, 3% or less of Mn, 0.2% or less of S, 10% or less of Ni, 30% or less of Cr, 6% or less of Cu, and 0.05-8% of Nb, the balance being substantially Fe and inevitable impurities, by mass.