Patents by Inventor Seiichi Mori
Seiichi Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9957241Abstract: A novel asymmetric diamine, diamino-2-(benzothiazole-2-yl)diphenyl ether, derivatives therefor, and an intermediate for the compound such as aminonitro-2-(benzothiazole-2-yl)diphenyl ether, dinitro-2-(benzothiazole-2-yl)diphenyl ether, and derivatives from these. Additionally, another novel asymmetric diamine, diamino-2-(benzoxazole-2-yl)diphenyl ether, derivatives therefor, and intermediate for the compound such as aminonitro-2-(benzoxazole-2-yl)diphenyl ether, dinitro-2-(benzoxazole-2-yl)diphenyl ether, and derivatives from these, and methods for preparing them.Type: GrantFiled: March 29, 2016Date of Patent: May 1, 2018Assignee: SEIKA CORPORATIONInventors: Motonori Takeda, Masahiro Kasamatsu, Akihiro Tamaki, Seiichi Mori, Mitsutaka Imoto, Yoshihisa Takeda
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Patent number: 9953129Abstract: In a first aspect the present invention is directed to a method of generating a scheme allowing classification of a cancer of an individual patient for estimating a clinical outcome for said patient. It also refers to a method of estimating a clinical outcome of a patient suffering from epithelial ovarian cancer (EOC). The present invention also refers to a method of determining whether the epithelial mesenchymal score of a patient suffering from a cancer can be changed by administering an EMT reversal agent to increase patients susceptibility for an anti-cancer treatment.Type: GrantFiled: September 24, 2012Date of Patent: April 24, 2018Assignees: Agency for Science, Technology and Research, National University of SingaporeInventors: Jean Paul Thiery, Yun-Ju Ruby Huang, Kian Ngiap Chua, Wen Jing Sim, Seiichi Mori
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Publication number: 20180079732Abstract: A novel asymmetric diamine, diamino-2-(benzothiazole-2-yl)diphenyl ether, derivatives therefor, and an intermediate for the compound such as aminonitro-2-(benzothiazole-2-yl)diphenyl ether, dinitro-2-(benzothiazole-2-yl)diphenyl ether, and derivatives from these. Additionally, another novel asymmetric diamine, diamino-2-(benzoxazole-2-yl)diphenyl ether, derivatives therefor, and intermediate for the compound such as aminonitro-2-(benzoxazole-2-yl)diphenyl ether, dinitro-2-(benzoxazole-2-yl)diphenyl ether, and derivatives from these, and methods for preparing them.Type: ApplicationFiled: March 29, 2016Publication date: March 22, 2018Applicant: SEIKA CORPORATIONInventors: Motonori TAKEDA, Masahiro KASAMATSU, Akihiro TAMAKI, Seiichi MORI, Mitsutaka IMOTO, Yoshihisa TAKEDA
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Publication number: 20150243670Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: ApplicationFiled: May 8, 2015Publication date: August 27, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Michiharu MATSUI, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Patent number: 9059300Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: GrantFiled: March 15, 2013Date of Patent: June 16, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Michiharu Matsui, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Publication number: 20140236495Abstract: In a first aspect the present invention is directed to a method of generating a scheme allowing classification of a cancer of an individual patient for estimating a clinical outcome for said patient. It also refers to a method of estimating a clinical outcome of a patient suffering from epithelial ovarian cancer (EOC). The present invention also refers to a method of determining whether the epithelial mesenchymal score of a patient suffering from a cancer can be changed by administering an EMT reversal agent to increase patients susceptibility for an anti-cancer treatment.Type: ApplicationFiled: September 24, 2012Publication date: August 21, 2014Inventors: Jean Paul Thiery, Yun-Ju Ruby Huang, Kian Ngiap Chua, Wen Jing Sim, Seiichi Mori
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Publication number: 20130270622Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: ApplicationFiled: March 15, 2013Publication date: October 17, 2013Inventors: Michiharu MATSUI, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Patent number: 8421143Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: GrantFiled: March 15, 2012Date of Patent: April 16, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Michiharu Matsui, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Patent number: 8405139Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: GrantFiled: April 13, 2011Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Michiharu Matsui, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Publication number: 20120168846Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: ApplicationFiled: March 15, 2012Publication date: July 5, 2012Inventors: Michiharu MATSUI, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Publication number: 20110186921Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: ApplicationFiled: April 13, 2011Publication date: August 4, 2011Inventors: Michiharu MATSUI, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Patent number: 7939406Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: GrantFiled: May 5, 2009Date of Patent: May 10, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Michiharu Matsui, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Patent number: 7795667Abstract: A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.Type: GrantFiled: July 3, 2003Date of Patent: September 14, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Iguchi, Katsuhiro Ishida, Hiroaki Tsunoda, Hirohisa Iizuka, Hiroaki Hazama, Seiichi Mori
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Patent number: 7785954Abstract: A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21a) in the cell array region, gate oxide film (21b) for a high-voltage circuit and gate oxide film (21c) for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film (22). After that, device isolation grooves (13) are formed and buried with a device isolation insulating film (14). The first-layer polycrystalline silicon film (24) is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film (24) is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film (22) and the second-layer polycrystalline silicon film (24).Type: GrantFiled: December 3, 2009Date of Patent: August 31, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Seiichi Mori
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Publication number: 20100081266Abstract: A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21a) in the cell array region, gate oxide film (21b) for a high-voltage circuit and gate oxide film (21c) for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film (22). After that, device isolation grooves (13) are formed and buried with a device isolation insulating film (14). The first-layer polycrystalline silicon film (24) is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film (24) is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film (22) and the second-layer polycrystalline silicon film (24).Type: ApplicationFiled: December 3, 2009Publication date: April 1, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Seiichi Mori
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Publication number: 20090221128Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: ApplicationFiled: May 5, 2009Publication date: September 3, 2009Inventors: Michiharu MATSUI, Seiichi MORI, Riichiro SHIROTA, Yuji TAKEUCHI, Takeshi KAMIGAICHI
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Patent number: 7573092Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: GrantFiled: November 2, 2006Date of Patent: August 11, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Michiharu Matsui, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Patent number: 7557401Abstract: A semiconductor device includes an element isolation insulating film adjacent to an active area, a gate insulating film formed on a semiconductor substrate in the active area, paired gate electrodes located on the gate insulating film, a contact plug located on the active area between the gate electrodes, a pair of first upper lines located on the gate electrodes, a second upper line located on the gate electrodes, and a stopper film above upper surfaces of the gate electrodes and side surfaces of the gate electrodes. The element isolation insulating film has a first height of an upper surface thereof with reference to an upper surface of the semiconductor substrate and a second height of another upper surface thereof with reference to another upper surface of the semiconductor substrate. The first height is smaller than the second height.Type: GrantFiled: April 18, 2006Date of Patent: July 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Keisuke Yonehama, Seiichi Mori, Eiji Sakagami, Masahisa Sonoda
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Patent number: 7538380Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: GrantFiled: November 3, 2006Date of Patent: May 26, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Michiharu Matsui, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Patent number: 7498630Abstract: A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.Type: GrantFiled: November 14, 2006Date of Patent: March 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ichige, Koji Hashimoto, Tatsuaki Kuji, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Koji Sakui