Abstract: A semiconductor integrated circuit device includes a memory block. The device performs a programming operation, a pre-programming operation, and an erasing operation. The pre-programming operation by which each of the nonvolatile memory cells in the erased state in the memory block including the nonvolatile memory cells is pre-programmed to an intermediate state between the programmed and erased states.

Abstract: A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.

Abstract: A semiconductor device is disclosed, which comprises trench type device isolation regions formed in a semiconductor substrate, semiconductor active regions electrically isolated by the isolation regions, a first electrode layer formed to self-align to the isolation regions, and a second electrode layer formed over the first electrode layer with an insulating film interposed therebetween, the top of each of the isolation regions being located, in an area where the second electrode layer is present, at a first level below the top of the first electrode layer and above the surface of the active regions and, in an area where the second electrode layer is not present, at a second level below the first level, and the surface of the active regions being at substantially the same level in the area where the second electrode layer is present and in the area where the second electrode layer is not present.

Abstract: A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.

Abstract: A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.

Abstract: A semiconductor device is disclosed, which comprises trench type device isolation regions formed in a semiconductor substrate, semiconductor active regions electrically isolated by the isolation regions, a first electrode layer formed to self-align to the isolation regions, and a second electrode layer formed over the first electrode layer with an insulating film interposed therebetween, the top of each of the isolation regions being located, in an area where the second electrode layer is present, at a first level below the top of the first electrode layer and above the surface of the active regions and, in an area where the second electrode layer is not present, at a second level below the first level, and the surface of the active regions being at substantially the same level in the area where the second electrode layer is present and in the area where the second electrode layer is not present.

Abstract: A non-volatile semiconductor memory device according to the present invention has a semiconductor substrate and a memory cell having a floating gate provided through a tunnel insulating layer on the semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate. The inter-insulating layer includes a silicon oxide layer contiguous to said floating gate, a first silicon nitride layer provided by a CVD method on the silicon oxide layer and a second silicon nitride layer provided on said first silicon nitride layer and having a lower trap density than that of the first silicon nitride layer. The inter-insulating layer may includes a silicon oxide layer contiguous to said floating gate and a silicon oxide layer deposited on said silicon oxide layer and having a quantity of hydrogen content on the order of 1019/cm3 or less.

Abstract: A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: A semiconductor device is disclosed, which comprises trench type device isolation regions formed in a semiconductor substrate, semiconductor active regions electrically isolated by the isolation regions, a first electrode layer formed to self-align to the isolation regions, and a second electrode layer formed over the first electrode layer with an insulating film interposed therebetween, the top of each of the isolation regions being located, in an area where the second electrode layer is present, at a first level below the top of the first electrode layer and above the surface of the active regions and, in an area where the second electrode layer is not present, at a second level below the first level, and the surface of the active regions being at substantially the same level in the area where the second electrode layer is present and in the area where the second electrode layer is not present.

Abstract: A non-volatile semiconductor memory device according to the present invention has a semiconductor substrate and a memory cell having a floating gate provided through a tunnel insulating layer on the semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate. The inter-insulating layer includes a silicon oxide layer contiguous to said floating gate, a first silicon nitride layer provided by a CVD method on the silicon oxide layer and a second silicon nitride layer provided on said first silicon nitride layer and having a lower trap density than that of the first silicon nitride layer. The inter-insulating layer may includes a silicon oxide layer contiguous to said floating gate and a silicon oxide layer deposited on said silicon oxide layer and having a quantity of hydrogen content on the order of 1019/cm3 or less.

Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.

Abstract: A semiconductor integrated circuit device includes a memory block. The device performs a programming operation, a pre-programming operation, and an erasing operation. The pre-programming operation by which each of the nonvolatile memory cells in the erased state in the memory block including the nonvolatile memory cells is pre-programmed to an intermediate state between the programmed and erased states.

Abstract: An enhanced non-volatile semiconductor memory has a source region and a drain region provided in a semiconductor substrate, an electric charge accumulating portion provided on a channel region between the source and drain regions and a control gate provided on said channel region and at least said source region is provided by introducing an impurity in self-alignment with a side wall provided on a side surface of said control gate, characterized in that an overlap of said drain region with said electric charge accumulating portion is set larger than an overlap of said source region with said electric charge accumulating portion, and an impurity dose quantity of said source region is larger than an impurity dose quantity of said drain region. The drain region may be formed by self alignment manner using a first side wall and the source region may be formed by self alignment manner using a second side wall formed on the first side wall.

Abstract: A memory-cell array and peripheral circuit elements are formed together on a semiconductor substrate. A first interlayer insulating film is formed, covering the memory-cell array region and peripheral circuit region of the substrate. A first layer of wires is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film, covering the wires of the first layer. A second layer of wires is formed on the second interlayer insulating film. A third interlayer insulating film is formed on the second interlayer insulating film, covering the wires of the second layer. The third interlayer insulating film is processed to have a flat upper surface. A third layer of wires is formed on only that part of the third interlayer insulating film, which lies above the peripheral circuit region. Thereafter, a passivation film is deposited on the third interlayer insulating film.

Abstract: The present invention provides a method and an apparatus for crushing and pulverizing tire chips roughly crushed to a size of 10 cm in length by completely separating to rubber components from iron components in a single crushing process. It is intended to extensively simplify the process to produce rubber powder from waste tires and to promote material recycling of the used tires. The method comprises the steps of catching the tire chips between monoaxial rotary blades 3 rotated within a casing 2 and fixed blades 4 and 4 fixed and arranged at opposed positions and maintaining a gap slightly larger than diameter of a piano wire 9 contained in the tires, rupturing only the rubber components without cutting piano wires and steel fibers, tearing and withdrawing rubber components by rotation of the rotary blade 3, and crushing while separating rubber components from iron components.

Abstract: This invention discloses a memory cell threshold voltage shift method effective for the erase or write sequence of a nonvolatile semiconductor memory. First, the threshold voltages VTH of a plurality of memory cells are shifted at once to a range whose upper limit is set to an erase verify voltage VEV. After this, the lower limit of the threshold voltages VTH shifted at once to the range is shifted to a first overerase verify voltage VOEV1 close to the erase verify voltage VEV. Then, the lower limit of the threshold voltages VTH shifted to the first overerase verify voltage VOEV1 to a second overerase verify voltage VOEV2 closer to the erase verify voltage VEV.

Abstract: A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor.

Abstract: A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.

Abstract: In a semiconductor memory device, first insulating films are formed on a semiconductor substrate. Element isolating layers are formed on the semiconductor substrate for isolating element forming regions set at regular intervals in the semiconductor substrate, such that the upper surface of the element isolating layers are located at a higher level than the upper surface of the semiconductor substrate. First conductive layers are formed at regular intervals on the first insulating films. A second insulating film is formed on the element isolating layers and the first insulating film. A second conductive layer, which has a lower surface with irregularities corresponding to the configurations of the element isolating layers and the first conductive layer, and a flat upper surface irrespective of the configurations of the element isolating films and the first conductive layer, is formed on the second insulating film.