Patents by Inventor Seiichi Omoto

Seiichi Omoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230247833
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of conductive layers containing molybdenum (Mo) are stacked to be spaced apart from each other in a first direction, a pillar structure including a semiconductor layer extending in the first direction in the stacked body, a partition structure extending in the first direction and in a second direction intersecting the first direction in the stacked body, and dividing the stacked body in a third direction intersecting the first and second directions, and a plurality of intermediate layers, each including a portion provided between the pillar structure and a corresponding one of the conductive layers, and containing a compound of molybdenum (Mo) and boron (B).
    Type: Application
    Filed: September 14, 2022
    Publication date: August 3, 2023
    Applicant: Kioxia Corporation
    Inventors: Hikari Tajima, Masayuki Kitamura, Seiichi Omoto
  • Publication number: 20230178393
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a container configured to contain a substrate, a heater configured to heat the substrate contained in the container, and an injector configured to feed gas to the substrate contained in the container. Furthermore, the injector includes a first layer having a tubular shape, and a second layer provided on a surface of the first layer, and having an emissivity of 0.5 or less.
    Type: Application
    Filed: June 10, 2022
    Publication date: June 8, 2023
    Applicant: Kioxia Corporation
    Inventors: Junya FUJITA, Takayuki MATSUI, Seiichi OMOTO
  • Patent number: 10490466
    Abstract: A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. The semiconductor manufacturing method includes forming a second film inside the cavities by a CVD method using first gas containing a component of the second film, detecting a first time point at which the second film blocks openings of the cavities in forming the second film, and ending forming of the second film at a second time point at which a predetermined time has elapsed from the first time point.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 26, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazumasa Ito, Seiichi Omoto, Takanobu Itoh, Ryota Nakanishi
  • Patent number: 10304743
    Abstract: A semiconductor device according to this embodiment includes a semiconductor layer, a plurality of diffusion layers in the semiconductor layer, a gate insulating film, a gate electrode, first contacts, and second contacts. The gate insulating film is on the semiconductor layer between the plurality of diffusion layers. The gate electrode is on the gate insulating film. The first contacts include silicide layers of the same material which are on the gate electrode and the diffusion layers respectively, and first metal layers on the silicide layers. The second contacts are on the first contacts.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 28, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Naomi Fukumaki, Masaaki Hatano, Seiichi Omoto
  • Publication number: 20180151457
    Abstract: A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. The semiconductor manufacturing method includes forming a second film inside the cavities by a CVD method using first gas containing a component of the second film, detecting a first time point at which the second film blocks openings of the cavities in forming the second film, and ending forming of the second film at a second time point at which a predetermined time has elapsed from the first time point.
    Type: Application
    Filed: January 24, 2018
    Publication date: May 31, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Kazumasa ITO, Seiichi OMOTO, Takanobu ITOH, Ryota NAKANISHI
  • Publication number: 20170352622
    Abstract: A semiconductor device according to this embodiment includes a semiconductor layer, a plurality of diffusion layers in the semiconductor layer, a gate insulating film, a gate electrode, first contacts, and second contacts. The gate insulating film is on the semiconductor layer between the plurality of diffusion layers. The gate electrode is on the gate insulating film. The first contacts include silicide layers of the same material which are on the gate electrode and the diffusion layers respectively, and first metal layers on the silicide layers. The second contacts are on the first contacts.
    Type: Application
    Filed: September 12, 2016
    Publication date: December 7, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Naomi FUKUMAKI, Masaaki HATANO, Seiichi OMOTO
  • Patent number: 9812398
    Abstract: According to an embodiment, a semiconductor memory device comprises: a memory string comprising a plurality of memory cells connected in series therein; and a contact electrically connected to one end of the memory string. The memory string comprises a plurality of control gate electrodes, and a semiconductor layer. The contact comprises a contact layer, the contact layer having a plate-like shape whose longer direction is a first direction parallel to the substrate, and the contact layer having its lower surface electrically connected to the one end of the semiconductor layer. Moreover, the contact layer includes a metal layer, a silicon based layer, and a second conductive layer. The metal layer includes tungsten. The silicon based layer includes a material including silicon. The second conductive layer covers side surfaces of the metal layer and the silicon based layer.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: November 7, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ming Hu, Toshiyuki Takewaki, Seiichi Omoto
  • Publication number: 20170062286
    Abstract: A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing method includes forming cavities in the first film. The semiconductor manufacturing method includes forming a second film inside the cavities by a CVD method using first gas containing a component of the second film, detecting a first time point at which the second film blocks openings of the cavities in forming the second film, and ending forming of the second film at a second time point at which a predetermined time has elapsed from the first time point.
    Type: Application
    Filed: February 3, 2016
    Publication date: March 2, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa ITO, Seiichi Omoto, Takanobu Itoh, Ryota Nakanishi
  • Publication number: 20170025434
    Abstract: A semiconductor memory device according to an embodiment comprises a stacked body, a semiconductor layer, a charge accumulation layer, and a slit portion. The stacked body includes a plurality of control gate electrodes stacked above a substrate. The semiconductor layer has one end thereof connected to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. The slit portion extends in a direction of the substrate from a surface of the stacked body, wherein the slit portion has its longitudinal direction in a direction intersecting the first direction.
    Type: Application
    Filed: January 8, 2016
    Publication date: January 26, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuaki NAKAJIMA, Seiichi OMOTO, Hiroshi TOYODA
  • Patent number: 9543321
    Abstract: A semiconductor memory device according to an embodiment comprises a stacked body, a semiconductor layer, a charge accumulation layer, and a slit portion. The stacked body includes a plurality of control gate electrodes stacked above a substrate. The semiconductor layer has one end thereof connected to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. The slit portion extends in a direction of the substrate from a surface of the stacked body, wherein the slit portion has its longitudinal direction in a direction intersecting the first direction.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: January 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuaki Nakajima, Seiichi Omoto, Hiroshi Toyoda
  • Publication number: 20160358762
    Abstract: In one embodiment, a semiconductor manufacturing system includes a gas supply module configured to supply an etching gas. The system further includes a chamber configured to house a substrate. The system further includes a metal member housing provided outside the chamber and configured to house a metal member, the metal member housing being configured to introduce the etching gas and to discharge a metal-containing gas that contains a metal etched from the metal member by the etching gas. Furthermore, the chamber is configured to introduce the metal-containing gas discharged from the metal member housing and to form a metal film on the substrate by the metal-containing gas.
    Type: Application
    Filed: August 26, 2015
    Publication date: December 8, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takayuki BEPPU, Kazuaki NAKAJIMA, Seiichi OMOTO
  • Patent number: 9514977
    Abstract: A semiconductor device according to the present embodiment includes a first wiring part located above a substrate and made of a first metal material. A second wiring part is provided as being superimposed on the first wiring part and having a width substantially equal to that of the first wiring part. A first resistivity of the first wiring part is lower than a second resistivity of the second wiring part when the first and second wiring parts have a first width. The second resistivity is lower than the first resistivity when the first and second wiring parts have a second width larger than the first width. The semiconductor device includes both of an area in which the first and second wiring parts have the first width and an area in which the first and second wiring parts have the second width.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: December 6, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiyuki Morita, Seiichi Omoto, Kazuaki Nakajima, Hiroshi Toyoda
  • Publication number: 20160268191
    Abstract: According to an embodiment, a semiconductor memory device comprises: a memory string comprising a plurality of memory cells connected in series therein; and a contact electrically connected to one end of the memory string. The memory string comprises a plurality of control gate electrodes, and a semiconductor layer. The contact comprises a contact layer, the contact layer having a plate-like shape whose longer direction is a first direction parallel to the substrate, and the contact layer having its lower surface electrically connected to the one end of the semiconductor layer. Moreover, the contact layer includes a metal layer, a silicon based layer, and a second conductive layer. The metal layer includes tungsten. The silicon based layer includes a material including silicon. The second conductive layer covers side surfaces of the metal layer and the silicon based layer.
    Type: Application
    Filed: September 9, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ming HU, Toshiyuki TAKEWAKI, Seiichi OMOTO
  • Publication number: 20160260734
    Abstract: In one embodiment, a semiconductor device includes a substrate, a semiconductor layer provided on the substrate, and plural insulators and plural interconnects alternately provided on a side face of the semiconductor layer. Each of the interconnects includes a first interconnect layer provided on the side face of the semiconductor layer, and having an upper face that is in contact with one of the insulators and a lower face that is in contact with one of the insulators. Each of the interconnects further includes a second interconnect layer provided on a side face of the first interconnect layer, and having an upper face that is in contact with one of the insulators and a lower face that is in contact with one of the insulators.
    Type: Application
    Filed: July 1, 2015
    Publication date: September 8, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki BEPPU, Kazuaki NAKAJIMA, Seiichi OMOTO
  • Publication number: 20150171003
    Abstract: A semiconductor device according to the present embodiment includes a first wiring part located above a substrate and made of a first metal material. A second wiring part is provided as being superimposed on the first wiring part and having a width substantially equal to that of the first wiring part. A first resistivity of the first wiring part is lower than a second resistivity of the second wiring part when the first and second wiring parts have a first width. The second resistivity is lower than the first resistivity when the first and second wiring parts have a second width larger than the first width. The semiconductor device includes both of an area in which the first and second wiring parts have the first width and an area in which the first and second wiring parts have the second width.
    Type: Application
    Filed: March 7, 2014
    Publication date: June 18, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiyuki MORITA, Seiichi OMOTO, Kazuaki NAKAJIMA, Hiroshi TOYODA
  • Patent number: 8922017
    Abstract: According to one embodiment, a semiconductor device includes a polysilicon film formed above a semiconductor substrate, and a silicide film of a metal formed on the polysilicon film. The semiconductor device of the embodiment includes an oxide film of the metal formed above the silicide film, and a film containing tungsten or molybdenum formed on the oxide film.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiichi Omoto
  • Patent number: 8912089
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Omoto, Yoshihiro Uozumi, Tadashi Iguchi, Osamu Yamane, Kazuyuki Masukawa, Yoshihiro Yanai
  • Publication number: 20140061752
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.
    Type: Application
    Filed: March 21, 2013
    Publication date: March 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Omoto, Yoshihiro Uozumi, Tadashi Iguchi, Osamu Yamane, Kazuyuki Masukawa, Yoshihiro Yanai
  • Publication number: 20130037876
    Abstract: According to one embodiment, a semiconductor device includes a polysilicon film formed above a semiconductor substrate, and a silicide film of a metal formed on the polysilicon film. The semiconductor device of the embodiment includes an oxide film of the metal formed above the silicide film, and a film containing tungsten or molybdenum formed on the oxide film.
    Type: Application
    Filed: March 9, 2012
    Publication date: February 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Seiichi OMOTO
  • Publication number: 20120152168
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 21, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma