Patents by Inventor Seiichi Watarai
Seiichi Watarai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8188779Abstract: The circuit includes a duty control buffer and a duty control voltage generator that receives outputs of the duty control buffer, detects a duty error, and generates control signals. The duty control buffer includes a differential stage including unbalanced first and second differential pairs each differentially receiving input signals, a load element pair connected between output pairs of the first and second differential pairs and a power supply, and a current source stage that supplies respective driving currents to the first and second differential pairs.Type: GrantFiled: December 10, 2009Date of Patent: May 29, 2012Assignee: Renesas Electronics CorporationInventor: Seiichi Watarai
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Patent number: 7924074Abstract: A delay control circuit in which steady phase error can be eliminated has a first variable delay circuit and a first phase control circuit. The delay control circuit further includes a second variable delay circuit disposed in either a first or second clock path, and a second phase control circuit arranged so as to form an additional feedback loop, which is for canceling steady phase error produced by the first phase control circuit, with respect to the first clock path or second clock path using a delay value applied to the second variable delay circuit.Type: GrantFiled: December 18, 2008Date of Patent: April 12, 2011Assignee: Renesas Electronics CorporationInventor: Seiichi Watarai
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Patent number: 7741875Abstract: A low amplitude differential output circuit includes a pre-buffer circuit configured to output a main buffer drive signal of a-first drive signal and a second drive signal which are complimentary signals, as a differential signal; and a main buffer circuit connected with the pre-buffer circuit to output a differential output signal in response to the main buffer drive signal. Each of the first drive signal and the second drive signal has an amplitude between a first voltage and a second voltage, and the first drive signal and the second drive signal take a same voltage between the first voltage and a middle voltage between the first voltage and the second voltage.Type: GrantFiled: February 28, 2006Date of Patent: June 22, 2010Assignee: NEC Electronics CorporationInventor: Seiichi Watarai
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Publication number: 20100148835Abstract: The circuit includes a duty control buffer and a duty control voltage generator that receives outputs of the duty control buffer, detects a duty error, and generates control signals. The duty control buffer includes a differential stage including unbalanced first and second differential pairs each differentially receiving input signals, a load element pair connected between output pairs of the first and second differential pairs and a power supply, and a current source stage that supplies respective driving currents to the first and second differential pairs.Type: ApplicationFiled: December 10, 2009Publication date: June 17, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Seiichi Watarai
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Patent number: 7573299Abstract: An output circuit includes a differential section configured to amplify an inputted differential signal; a current source section configured to supply a current to the differential section; a load resistance section connected with the differential section; and a control unit configured to set a value of the current from the current source section and a resistance value of the load resistance section based on a signal supplied to the control unit. The output circuit converts the differential signal into an output signal of a different interface level from that of the differential signal and balance-transmits the output signal.Type: GrantFiled: May 29, 2007Date of Patent: August 11, 2009Assignee: NEC Electronics CorporationInventor: Seiichi Watarai
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Publication number: 20090160512Abstract: A delay control circuit in which steady phase error can be eliminated has a first variable delay circuit and a first phase control circuit. The delay control circuit further includes a second variable delay circuit disposed in either a first or second clock path, and a second phase control circuit arranged so as to form an additional feedback loop, which is for canceling steady phase error produced by the first phase control circuit, with respect to the first clock path or second clock path using a delay value applied to the second variable delay circuit.Type: ApplicationFiled: December 18, 2008Publication date: June 25, 2009Applicant: NEC Electronics CorporationInventor: Seiichi Watarai
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Publication number: 20070279124Abstract: An output circuit includes a differential section configured to amplify an inputted differential signal; a current source section configured to supply a current to the differential section; a load resistance section connected with the differential section; and a control unit configured to set a value of the current from the current source section and a resistance value of the load resistance section based on a signal supplied to the control unit. The output circuit converts the differential signal into an output signal of a different interface level from that of the differential signal and balance-transmits the output signal.Type: ApplicationFiled: May 29, 2007Publication date: December 6, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Seiichi Watarai
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Patent number: 7245155Abstract: A data output circuit is composed of first and second differential MOS transistors, first and second cascade MOS transistors, first and second outputs, and first and second resistor elements. The first and second differential MOS transistors receive first and second input voltages on the gates, respectively, sources of the differential MOS transistors being commonly connected. The first cascade MOS transistor is connected between the first differential MOS transistor and the first output, and the second cascade MOS transistor is connected between the second differential MOS transistor and the second output, gates of the first and second cascade MOS transistors being commonly connected. The first transistor element is connected between a ground line and the commonly connected gates, and the second transistor element is connected between a power supply line and the commonly connected gates.Type: GrantFiled: March 25, 2005Date of Patent: July 17, 2007Assignee: NEC Electronics CorporationInventor: Seiichi Watarai
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Patent number: 7164743Abstract: A delay locked loop of the present invention which synthesizes data and a clock inputted from outside has: voltage control delay loops having a plurality of delay circuit parts sequentially delaying the clock; a slot selector selecting a slot outputted from the delay circuit parts of the voltage control delay loops; a clock tree part creating a plurality of clocks with the same timing by an output of the slot selector; a phase control part phase-controlling the plurality of delay circuit parts corresponding to the output clock delay variation of the clock tree part; and sensing means on-off controlling all or part of the plurality of delay circuit parts and the slot selector.Type: GrantFiled: September 12, 2002Date of Patent: January 16, 2007Assignee: NEC Electronics CorporationInventor: Seiichi Watarai
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Publication number: 20060214717Abstract: A low amplitude differential output circuit includes a pre-buffer circuit configured to output a main buffer drive signal of a-first drive signal and a second drive signal which are complimentary signals, as a differential signal; and a main buffer circuit connected with the pre-buffer circuit to output a differential output signal in response to the main buffer drive signal. Each of the first drive signal and the second drive signal has an amplitude between a first voltage and a second voltage, and the first drive signal and the second drive signal take a same voltage between the first voltage and a middle voltage between the first voltage and the second voltage.Type: ApplicationFiled: February 28, 2006Publication date: September 28, 2006Applicant: NEC Electronics CorporationInventor: Seiichi Watarai
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Patent number: 6967505Abstract: An input circuit includes a data input unit for receiving input data of the input circuit. A data latch unit latches output data of the input circuit. A reset unit resets the data latch unit in response to a first logic level of a first clock signal. A latch enhancement unit enhances the latching operation of the data latch unit in response to a first logic level of a second clock signal that is delayed in phase from the first clock signal. A clock synchronization unit transfers the input data from the input unit to the data latch unit in response to a second logic level of the first clock signal, the clock synchronization unit blocking a feedthrough current that flows through the reset unit, the data latch unit, and the latch enhancement unit when the first and second clock signals are in a first logic level state.Type: GrantFiled: October 31, 2003Date of Patent: November 22, 2005Assignee: NEC Electronics CorporationInventor: Seiichi Watarai
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Publication number: 20050218935Abstract: A data output circuit is composed of first and second differential MOS transistors, first and second cascade MOS transistors, first and second outputs, and first and second resistor elements. The first and second differential MOS transistors receive first and second input voltages on the gates, respectively, sources of the differential MOS transistors being commonly connected. The first cascade MOS transistor is connected between the first differential MOS transistor and the first output, and the second cascade MOS transistor is connected between the second differential MOS transistor and the second output, gates of the first and second cascade MOS transistors being commonly connected. The first transistor element is connected between a ground line and the commonly connected gates, and the second transistor element is connected between a power supply line and the commonly connected gates.Type: ApplicationFiled: March 25, 2005Publication date: October 6, 2005Applicant: NEC Electronics CorporationInventor: Seiichi Watarai
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Patent number: 6900679Abstract: The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL1 in which differential buffers G1-G10 having a propagation delay time of 160 ps are concatenated in a plurality of stages; voltage-controlled delay line VCDL2 in which differential buffers H1-H8 having a propagation delay time of 200 ps are concatenated in a plurality of stages; selector S2 that extracts a clock signal from any stage of voltage-controlled delay line VCDL1 and outputs to the first stage of voltage-controlled delay line VCDL2; and selector S3 that extracts and outputs a clock signal from any stage of voltage-controlled delay line VCDL2.Type: GrantFiled: July 10, 2002Date of Patent: May 31, 2005Assignee: NEC Electronics CorporationInventor: Seiichi Watarai
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Patent number: 6771114Abstract: A charge pump current compensating circuit (4) including feedback so that a difference between a charging current and a discharging current may be reduced is disclosed. Charge pump current compensating circuit (4) may include a current source leg (I11, N16, and N15), a first current mirror leg (P13, P14, N14, and N13), a second current mirror leg (P11, P12, N12, and N11), and a compensation circuit (5). Compensation circuit (5) may provide compensation to control insulated gate field effect transistors (IGFETs) (P12 and P13) so that a charging current and a discharging current may be essentially the same even when output impedances of IGFETs (P12 and N12) are different.Type: GrantFiled: September 9, 2002Date of Patent: August 3, 2004Assignee: NEC Electronics CorporationInventor: Seiichi Watarai
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Publication number: 20040090251Abstract: An input circuit according to the present invention has a data input means for the input of input data; a data latch means for latching the input data; a reset means for resetting the data latch means; a clock synchronization means for synchronizing the input of the input data to the data input means; and a latch enhancement means for blocking feedthrough current by functioning complementarily to the reset means, and enhancing the latching operation of the data latch means.Type: ApplicationFiled: October 31, 2003Publication date: May 13, 2004Applicant: NEC Electronics CorporationInventor: Seiichi Watarai
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Patent number: 6642748Abstract: An input circuit includes a data input unit for the input of input data, a data latch for latching the input data, a reset unit for resetting the data latch, a clock synchronization unit for synchronizing the input of the input data to the data input unit, and a latch enhancement unit for blocking feedthrough current by functioning complementarily to the reset unit, and enhancing the latching operation of the data latch.Type: GrantFiled: March 21, 2002Date of Patent: November 4, 2003Assignee: NEC Electronics CorporationInventor: Seiichi Watarai
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Publication number: 20030053577Abstract: A delay locked loop of the present invention which synthesizes data and a clock inputted from outside has: voltage control delay loops having a plurality of delay circuit parts sequentially delaying the clock; a slot selector selecting a slot outputted from the delay circuit parts of the voltage control delay loops; a clock tree part creating a plurality of clocks with the same timing by an output of the slot selector; a phase control part phase-controlling the plurality of delay circuit parts corresponding to the output clock delay variation of the clock tree part; and sensing means on-off controlling all or part of the plurality of delay circuit parts and the slot selector.Type: ApplicationFiled: September 12, 2002Publication date: March 20, 2003Applicant: NEC CORPORATIONInventor: Seiichi Watarai
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Publication number: 20030048126Abstract: A charge pump current compensating circuit (4) including feedback so that a difference between a charging current and a discharging current may be reduced is disclosed. Charge pump current compensating circuit (4) may include a current source leg (I11, N16, and N15), a first current mirror leg (P13, P14, N14, and N13), a second current mirror leg (P11, P12, N12, and N11), and a compensation circuit (5). Compensation circuit (5) may provide compensation to control insulated gate field effect transistors (IGFETs) (P12 and P13) so that a charging current and a discharging current may be essentially the same even when output impedances of IGFETs (P12 and N12) are different.Type: ApplicationFiled: September 9, 2002Publication date: March 13, 2003Inventor: Seiichi Watarai
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Publication number: 20030001638Abstract: The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL1 in which differential buffers G1-G10 having a propagation delay time of 160 ps are concatenated in a plurality of stages; voltage-controlled delay line VCDL2 in which differential buffers H1-H8 having a propagation delay time of 200 ps are concatenated in a plurality of stages; selector S2 that extracts a clock signal from any stage of voltage-controlled delay line VCDL1 and outputs to the first stage of voltage-controlled delay line VCDL2; and selector S3 that extracts and outputs a clock signal from any stage of voltage-controlled delay line VCDL2.Type: ApplicationFiled: July 10, 2002Publication date: January 2, 2003Applicant: NEC CorporationInventor: Seiichi Watarai
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Patent number: 6492851Abstract: The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL1 in which differential buffers (G1-G10) having a propagation delay time of 160 ps are concatenated in a plurality of stages; voltage-controlled delay line (VCDL2) in which differential buffers (H1-H8) having a propagation delay time of 200 ps are concatenated in a plurality of stages; selector (S2) that extracts a clock signal from any stage of voltage-controlled delay line (VCDL1) and outputs to the first stage of voltage-controlled delay line (VCDL2); and selector S3 that extracts and outputs a clock signal from any stage of voltage-controlled delay line (VCDL2).Type: GrantFiled: March 29, 2001Date of Patent: December 10, 2002Assignee: NEC CorporationInventor: Seiichi Watarai