Abstract: An input circuit according to the present invention has a data input means for the input of input data; a data latch means for latching the input data; a reset means for resetting the data latch means; a clock synchronization means for synchronizing the input of the input data to the data input means; and a latch enhancement means for blocking feedthrough current by functioning complementarily to the reset means, and enhancing the latching operation of the data latch means.

Abstract: There is provided a signal transmission system, wherein when a control signal which puts an output terminal of an output circuit 12A into a high-impedance state is supplied to the output circuit 12A and an input circuit 14A, power is fed to the input circuit 12A to operate it and, at the same time, power-feeding to the output circuit 12A is stopped; and when the control signal is not supplied to the output circuit 12A nor the input circuit 14A, power is fed to the output circuit 12A to operate it and, at the same time, power-feeding to the input circuit 12A is stopped. Also, a signal of an expected value of the output circuit 12A based on the control signal is generated from an OR circuit 45.

Abstract: A transient current producing method, a transient producing circuit, a related semiconductor integrated circuit and logical circuit are provided, which are capable of preventing a flow of a steady state current, consuming little power and switching at high speed. A transient current occurring at a time of switching of a CMOS circuit is amplified to a predetermined value. This amplification prevents the flow of the steady state current in the circuit. The transient current occurring at the time of switching of the CMOS circuit is converted to a transient voltage. The conversion of the transient current to the transient voltage having a predetermined value and the amplification of the transient current allow a simple configuration of the circuit. The transient current is a feedthrough current which flows from a terminal of a power supply to a ground at the time of switching of the CMOS circuit.

Abstract: A differential tri-state circuit in which noise picked up by an output signal can be removed. The differential tri-state circuit is so configured that, by allowing the same currents to flow from a current source to a p-channel MOS FET and an n-channel MOS FET and to other p-channel MOS FET and other n-channel MOS FET, high impedance state exists between output terminals. With the p-channel MOS FET and the n-channel MOS FET being brought into conduction and with other p-channel MOS FET and other n-channel MOS FET being brought out of conduction, by causing terminating resistors RT1 and RT2 to be conducting or by bringing about a state being in reverse to the above, a 0 state or 1 state is outputted between output terminals.

Abstract: The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL1 in which differential buffers G1-G10 having a propagation delay time of 160 ps are concatenated in a plurality of stages; voltage-controlled delay line VCDL2 in which differential buffers H1-H8 having a propagation delay time of 200 ps are concatenated in a plurality of stages; selector S2 that extracts a clock signal from any stage of voltage-controlled delay line VCDL1 and outputs to the first stage of voltage-controlled delay line VCDL2; and selector S3 that extracts and outputs a clock signal from any stage of voltage-controlled delay line VCDL2.

Abstract: An input-output circuit in which, even if variations in logic threshold voltages occurs, a logic signal can be exactly recognized on the basis of small-amplitude signals supplied.

Abstract: A level shifting circuit comprises a first insulated-gate transistor which has its gate provided with an input signal and a second insulated-gate transistor which has its drain connected with the source of the first insulated-gate transistor. The second insulated-gate transistor may have the same conductivity type as the first insulated-gate transistor. A voltage not affected by factors such as the manufacturing process used to make the device, operating temperature, or supply voltage is applied to the gate of the second insulated-gate transistor. A ratio of gate channel width to gate channel length for these two insulated-gate transistors are set to a same value, thereby allowing the level-shifting circuit to output a constant predetermined value; and which is not affected by the aforementioned manufacturing process, operating temperature, and supply voltage factors.

Abstract: To provide an input circuit of an IC wherein the current flowing towards the input terminal when receiving a LOW level signal can be restricted to minimum, and the input threshold level can be controlled appropriately without degrading transition performance of the input circuit, an input circuit includes: a current control means for controlling a first current to be supplied to a first node according to a second current to be supplied to a second node an input level transfer means for transferring logic of the external logical signal into an intermediate signal whereof potential of a HIGH level is restricted within a power supply voltage; a level shift means for shifting a LOW level of the intermediate signal to substantially the same level of a LOW level of the external logical signal; an inverter for outputting a signal of low output impedance by inverting the shifted intermediate signal; and a transition current generating means for controlling the level shift means to supply a sufficient transition curre

Abstract: In an emitter follower circuit, a bipolar transistor is connected to a resistor element. The bipolar transistor has a temperature dependent characteristic. A current source circuit is connected to the resistor element to flow a current through the resistor element such that a voltage drop by the resistor element has an opposite temperature dependent characteristic to the first temperature dependent characteristic of the bipolar transistor.

Abstract: A small amplitude signal output circuit comprises an output section, for receiving a logic signal to output a small amplitude signal, having first and second transistors connected in series between a first source line and a second source line, and voltage control sections connected between each of the source lines and the output section for reducing the output voltage supplied from the output node, thereby allowing ON-resistance of the transistors of the output section to be smaller. The small ON-resistance of the transistors in turn allows variations in the output voltage of the output circuit caused by variations in the fabrication process to be smaller. The voltage control sections may have a function for reducing variations in the output circuit due to temperature variation.

Abstract: A small amplitude signal output circuit comprises an output section for receiving a logic signal to output a small amplitude signal, a level sense circuit for sensing the rise or fall of an output voltage at an output terminal, and a level control circuit for responding to the output of the level sense circuit to suppress the rise or fall of the output voltage. The output circuit suppresses voltage variations caused by variations in fabrication process of transistors, ambient temperature and source voltage noise.

Abstract: According to the present invention, an input circuit is provided comprising: an input terminal; a first power source terminal; a second power source terminal; a first bipolar transistor; a second bipolar transistor; a first electric current cut off member; a second electric current cut off member; a voltage clamping member; and a buffer. As a result, even when an electric potential greater than that of the power source voltage is applied to the input terminal, regardless of the supply or interruption of the power source voltage, destruction of the internal components is prevented and a steady-state electric current of the power source voltage and/or the input terminal is cut off. Hence, providing a PMOS transistor and NMOS transistor, serves to cut off the electric current routes of power source terminal VDD and the ground terminal.

Abstract: A tristate buffer comprises an output block having a pair of NPN bipolar transistor and nMOS transistor between the source line and ground line and connected to each other at the output terminal of the tristate buffer. The tristate buffer has a base potential control block for discharging the base of the NPN transistor and to couple the base to the output terminal of the tristate buffer during an initial stage of the high-impedance state. After the initial stage of the high-impedance state, the base and output terminal are disconnected from each other. A reverse bias overvoltage occurring in the base-to-emitter P-N junction and a current flow during the high-impedance state are eliminated.

Abstract: A first capacitor 7, a resistor 5, and a second capacitor 6 are connected in series between an output node A and a first power supply line 22. In addition, a first switch 8 is connected between the connected point of the first capacitor 7 and the resistor 5 and a second power supply line. A second switch 9 is connected in parallel with the second capacitor 6. The first and second switches 8 and 9 are opened or closed corresponding to the level of the input signal.

Abstract: An output circuit comprises a transfer gate connected between an input terminal of the output circuit and an input of an output buffer circuit, a protection circuit for turning off a transistor constituting the output buffer when a potential higher than an operating source voltage of the output buffer circuit is applied to an output of the output buffer circuit, and a control circuit for turning on the transfer gate in response to a signal input to the input terminal and to turn for turning off the transfer gate when the protection circuit is actuated.

Abstract: A variable delay circuit for arbitrarily change of a signal delay helps easily attain a desired resolution with a high precision, which has been difficult due to device process dependence of a voltage control circuit applying a voltage to a CMOS circuit. A variable voltage controller is provided between a power source and a CMOS circuit propagating a signal such that a delay time of signal propagation is supervised by controlling the voltage at a connecting point in the variable voltage controller. The controller includes two MOS transistors and an npn transistor, which solves the process dependence and hence leads to a low power consumption and a high resolution.

Abstract: In order to effectively interface a plurality of integrated circuits to a bus, an improved driver is disclosed. The driver includes an inverter provided between a power source and a ground level, and an output transistor whose gate is coupled to an output of the inverter and whose source-drain path is coupled between an output of the driver and the second power source. A feedback path is coupled between the output of the driver and the output of the inverter. The feedback path includes first and second transistors coupled in series. The first transistor has its gate coupled to an input of the inverter, while the second transistor has its gate coupled to the output of the inverter via delay means. The driver is characterized by an impedance controller which is provided between the output of the inverter and the second power source. The impedance controller stepwisely adjusts impedance of the output transistor when an input signal to the inverter changes from a low logic level to a high logic level.

Abstract: In a GTL circuit for restraining a ringing occurred by parasitic active elements on a package and a transmission path, the GTL circuits comprises two NMOS transistors connected in series to each other, for restraining a ringing between the gate and drain of an open drain type NMOS transistor which drives an output potential, and a plurality of delay circuits connected in series, for controlling periodically a current flowing through the two NMOS transistors, thereby reducing the ringing exceedingly the ringing caused by extremely large inductive elements which are connected to an output terminal as loads, and achieving a high speed operation of the GTL circuit.