Patents by Inventor Seiichiro Kobayashi

Seiichiro Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7439550
    Abstract: A semiconductor light emitting device can be configured to prevent diffusion migration of components constituting a linear electrode. The semiconductor light emitting device can include a substrate, at least one semiconductor layer formed on the substrate and having a topmost semiconductor layer, a pad electrode formed from a plurality of layers provided on the topmost semiconductor layer, and a linear electrode provided on the topmost semiconductor layer. The linear electrode can be configured to overlap the topmost semiconductor layer except for an area occupied by the pad electrode. The linear electrode can also be configured to make contact with part of the pad electrode, and form an ohmic contact with the topmost semiconductor layer. The pad electrode can include, as one of the plurality of layers, a barrier metal layer that covers part of or all of an upper surface and/or a sidewall of the linear electrode at a contact area between the linear electrode and the pad electrode.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: October 21, 2008
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Yuko Tomioka, Seiichiro Kobayashi, Kazuki Takeshima
  • Patent number: 7429754
    Abstract: A LED chip having first and second electrodes on opposite principal surfaces, is bonded to a substrate through a composite bonding layer. The composite bonding layer is formed when a support substrate including the substrate and a first bonding layer is bonded to a lamination structure including the LED, the first electrode and a second bonding layer. The first or second bonding layer contains at least part of eutectic composition. At least one of the support substrate and the lamination structure includes a diffusion material layer. The composite bonding layer is formed in such a manner that eutectic material contents are mixed with the other to form a first mixture, and that the first mixture is mixed with diffusion material to form a second mixture having a melting point higher than a melting point of the first mixture.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: September 30, 2008
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Junichi Sonoda, Seiichiro Kobayashi, Kazuyuki Yoshimizu
  • Publication number: 20080169481
    Abstract: A semiconductor light emitting device including: a support substrate; a composite connection layer formed above the support substrate, the composite connection layer including a first connection layer and a second connection layer; a diffusion barrier layer formed above the composite connection layer; a semiconductor lamination structure formed above the diffusion barrier layer; and a reflective electrode layer formed between the diffusion barrier layer and the semiconductor lamination structure, wherein: at least one of the first and second connection layers is made of eutectic material; and the diffusion barrier layer has a lamination structure having TaN layers sandwiching at least one refractory metal layer made of one or more refractory metal materials of Ta, Ti, Mo, W and TiW or alloy thereof. It is possible to prevent defects such as stripping and cracks at bonding planes and improve reliability of a final semiconductor light emitting device.
    Type: Application
    Filed: October 4, 2007
    Publication date: July 17, 2008
    Applicant: Stanley Electric Co., Ltd.
    Inventors: Seiichiro Kobayashi, Kazuyuki Yoshimizu
  • Publication number: 20060197099
    Abstract: A semiconductor light emitting device can be configured to prevent diffusion migration of components constituting a linear electrode. The semiconductor light emitting device can include a substrate, at least one semiconductor layer formed on the substrate and having a topmost semiconductor layer, a pad electrode formed from a plurality of layers provided on the topmost semiconductor layer, and a linear electrode provided on the topmost semiconductor layer. The linear electrode can be configured to overlap the topmost semiconductor layer except for an area occupied by the pad electrode. The linear electrode can also be configured to make contact with part of the pad electrode, and form an ohmic contact with the topmost semiconductor layer. The pad electrode can include, as one of the plurality of layers, a barrier metal layer that covers part of or all of an upper surface and/or a sidewall of the linear electrode at a contact area between the linear electrode and the pad electrode.
    Type: Application
    Filed: March 2, 2006
    Publication date: September 7, 2006
    Inventors: Yuko Tomioka, Seiichiro Kobayashi, Kazuki Takeshima
  • Publication number: 20060057817
    Abstract: A LED chip having first and second electrodes on opposite principal surfaces, is bonded to a substrate through a composite bonding layer. The composite bonding layer is formed when a support substrate including the substrate and a first bonding layer is bonded to a lamination structure including the LED, the first electrode and a second bonding layer. The first or second bonding layer contains at least part of eutectic composition. At least one of the support substrate and the lamination structure includes a diffusion material layer. The composite bonding layer is formed in such a manner that eutectic material contents are mixed with the other to form a first mixture, and that the first mixture is mixed with diffusion material to form a second mixture having a melting point higher than a melting point of the first mixture.
    Type: Application
    Filed: August 16, 2005
    Publication date: March 16, 2006
    Applicant: Stanley Electric Co., Ltd.
    Inventors: Junichi Sonoda, Seiichiro Kobayashi, Kazuyuki Yoshimizu
  • Publication number: 20040183634
    Abstract: An electromagnetic relay includes a first electromagnetic block provided with a movable contact, a normally open contact and a normally closed contact, and a second electromagnetic block provided with at least a movable contact and a normally open contact, both the first electromagnetic block and the second electromagnetic block being placed in a single case, wherein the normally closed contact of the first electromagnetic block is connected to the movable contact of the second electromagnetic block within the case.
    Type: Application
    Filed: October 3, 2003
    Publication date: September 23, 2004
    Inventors: Seiichiro Kobayashi, Tomohiro Maeta
  • Patent number: 6664549
    Abstract: In a wafer chuck for flatly vacuum-chucking a semiconductor wafer (11) supported by support pins (15) such that a pressure in a suction chamber (13) surrounded by an external wall (12), the upper surface of the external wall (12) is formed to be lower than the upper surfaces of the support pins, and the upper surface of the external wall (12) does not pressure the semiconductor wafer (11), a distance (L1) between the external wall (12) and closest support pins (15a) is up to 1.8 mm, and an alignment pitch. (L2) of the support pins (15) aligned inside the closest support pins (15a) to the external wall (12) is not more than 1.5 times of the distance (L1) between the external wall (12) and the closest support pins (15a).
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: December 16, 2003
    Assignee: Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Seiichiro Kobayashi, Koichi Koyanagi, Teruo Honda, Hideo Saeki, Masaharu Motohashi
  • Publication number: 20030001103
    Abstract: In a wafer chuck for flatly vacuum-chucking a semiconductor wafer (11) supported by support pins (15) such that a pressure in a suction chamber (13) surrounded by an external wall (12), the upper surface of the external wall (12) is formed to be lower than the upper surfaces of the support pins, and the upper surface of the external wall (12) does not pressure the semiconductor wafer (11), a distance (L1) between the external wall (12) and closest support pins (15a) is up to 1.8 mm, and an alignment pitch (L2) of the support pins (15) aligned inside the closest support pins (15a) to the external wall (12) is not more than 1.5 times of the distance (L1) between the external wall (12) and the closest support pins (15a).
    Type: Application
    Filed: July 29, 2002
    Publication date: January 2, 2003
    Inventors: Seiichiro Kobayashi, Koichi Koyanagi, Teruo Honda, Hideo Saeki, Masaharu Motohashi
  • Patent number: 6002189
    Abstract: A stator core has 3N salient poles arranged circularly where N is a natural number of four or more but except a multiple of three. Coils are formed around the salient poles where winding directions of the coils is the same for the salient poles. A first, a second and a third crossover are formed between a first and an (N+1)-th salient pole, between the (N+1)-th and a (2N+1)-th salient pole and between the (2N+1)-th and the first salient pole, respectively, to forming a triangle before cutting within the salient poles arranged circularly. An end portion of each crossover is connected to a substrate.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: December 14, 1999
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Yasuo Oishi, Seiichiro Kobayashi, Hiroshi Muramatsu, Hidetoshi Kajiwara
  • Patent number: 4338145
    Abstract: A chrome-tantalum thin film resistor having a chrome-tantalum alloy thin film containing 10 to 95 atomic % of chrome. By subjecting this chrome-tantalum alloy thin film to heat treatment at temperatures not higher than 900.degree. C., a stable resistor can be obtained. Alternatively, by forming the chrome-tantalum alloy thin film on a substrate which is preheated at temperatures not higher than 900.degree. C., the temperature coefficient of resistance of the resistor can be improved so that a stable resistor can be obtained.
    Type: Grant
    Filed: December 15, 1980
    Date of Patent: July 6, 1982
    Assignee: Taisei Kohki Co., Ltd.
    Inventors: Nobuo Yasujima, Natsuo Itokawa, Seiichiro Kobayashi
  • Patent number: 4223754
    Abstract: An instrument panel device for automobiles, particularly cars, wherein the space on the rear side of the instrument panel is employed to provide air conduits for feeding conditioned air to the interior of the automobile. A closing plate is employed to close the space on the rear side of the instrument panel, and the closed space is vertically sectioned with a partition plate to provide two systems of air conduit passages which are insulated from each other. The respective air conduit passages communicate with blowing ports provided on the front surface of the instrument panel, with defroster blowing ports, and with side defogger blowing ports.
    Type: Grant
    Filed: March 30, 1978
    Date of Patent: September 23, 1980
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Hiroshi Mizuno, Seiichiro Kobayashi