Abstract: Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.

Abstract: Bus/memory bandwidth consumption caused by reading of auxiliary information not included in compressed data is reduced. A memory stores compressed data and auxiliary information used to read the compressed data. A semiconductor device includes a cache in which auxiliary information stored in the memory is stored, a control unit which, when a read request for reading compressed data stored in the memory is received, reads from the cache auxiliary information about the compressed data, if stored in the cache, or reads the auxiliary information about the compressed data, if not stored in the cache, from the memory and stores the auxiliary information about the compressed data in the cache, and which reads the compressed data from the memory using the auxiliary information about the compressed data, and an expansion unit to expand the compressed data read from the memory.

Abstract: Regarding association between an area where compressed data is stored and an area where auxiliary information required to access the compressed data is stored, it is necessary to manage the association by software for each processing unit, so that the processing becomes complicated. A management unit memory area including a compressed data storage area and an auxiliary information storage area including auxiliary information are defined on a memory space. By calculating an auxiliary information address from an address indicating a location on a memory where a management unit memory space is set, an address of the auxiliary information storage area, and an address of the compressed data, the compressed data and the auxiliary information are associated with each other and the auxiliary information is read.

Abstract: There is a problem that memory protection against access to a shared memory by a sub-arithmetic unit used by a program executed in a main-arithmetic unit cannot be performed in a related-art semiconductor device. According to one embodiment, a semiconductor device includes a sub-arithmetic unit configured to execute a process of a part of a program executed by a main-arithmetic unit, and a shared memory shared by the main-arithmetic unit and the sub-arithmetic unit, in which the sub-arithmetic unit includes a memory protection unit configured to permit or prohibit access to the shared memory based on an access permission range address value provided from the main-arithmetic unit, the access to the shared memory being access that arises from a process executed by the sub-arithmetic unit.

Abstract: Bus/memory bandwidth consumption caused by reading of auxiliary information not included in compressed data is reduced. A memory stores compressed data and auxiliary information used to read the compressed data. A semiconductor device includes a cache in which auxiliary information stored in the memory is stored, a control unit which, when a read request for reading compressed data stored in the memory is received, reads from the cache auxiliary information about the compressed data, if stored in the cache, or reads the auxiliary information about the compressed data, if not stored in the cache, from the memory and stores the auxiliary information about the compressed data in the cache, and which reads the compressed data from the memory using the auxiliary information about the compressed data, and an expansion unit to expand the compressed data read from the memory.

Abstract: Making effective use of an image encoder and an image decoder for processing a color image of a general-purpose standard bit depth, an image transmission device capable of transmitting/receiving a monochrome image of a higher bit depth is configured. An image transmission device includes an image encoder to encode a high bit-depth monochrome image and output encoded data and an image decoder to generate, by decoding the encoded data received via a transmission path, a high bit-depth monochrome image. The image encoder decomposes the input high bit-depth image data into plural bit planes corresponding to color image data of a standard bit depth and encodes the standard bit-depth color image data. The image decoder decodes the color image data of the standard bit depth and synthesizes, from the decoded standard bit-depth color image data, a high bit-depth monochrome image.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: A video encoding circuit includes a prediction image generation unit configured to receive a plurality of pictures, each of the pictures containing a plurality of components, search for a reference image from components of a picture itself or an already-encoded picture stored in a reference memory, and generate a prediction image based on information on a pixel contained in the reference image, the plurality of components corresponding to respective color components contained in the input picture and having wavelengths different from each other, the reference image being used for encoding of each of the plurality of components contained in the input picture, and an encoding unit configured to generate a bit stream based on the prediction image output from the prediction image generation unit, in which the prediction image generation unit outputs a reference component index indicating information on a component containing the reference image.

Abstract: A video decoding processing apparatus which can reduce overhead for the start of parallel decoding processing. The video decoding processing apparatus includes a parsing unit, and first and second video processing units. A coding bit stream including information of largest coding units each having at least a prescribed pixel size is supplied to an input terminal of the parsing unit. The parsing unit performs parsing of the syntax of the coding bit stream to thereby generate parallel-processable first and second intermediate streams from the largest coding unit. The first and second video processing units parallel-process the first and second intermediate streams generated from the parsing unit.

Abstract: A video encoding/decoding system includes a video encoding device, and a video decoding device. The video encoding device includes an encoding circuit for encoding an image including a diagnostic image or a normal image. The video decoding device includes a decoding circuit for decoding the image encoded in the encoding circuit, a check signal generation circuit for generating a check signal of the decoded image, a storage circuit for storing the check signal generated by the check signal generation circuit, and a comparison circuit for comparing the check signal stored in the storage circuit with the check signal generated by the check signal generation circuit. The failure is detected by comparing the check signal including an expected value stored in the storage circuit with the check signal including a comparison value generated by the check signal generation circuit by processing the same image data a plurality of times.

Abstract: In a picture encoding device and a picture decoding device, the access to a reference frame memory is suppressed. The picture encoding device is comprised of a first encoder for intra picture encoding, a second encoder for inter picture encoding, and an intermediate buffer. A local decoded picture generated by the first encoder is stored as a reference picture in the intermediate buffer, and the inter picture encoding by the second encoder is performed by referring to the local decoded picture in the intermediate buffer. A picture decoding device is comprised of a first decoder for intra picture decoding, a second decoder for inter picture decoding, and an intermediate buffer. A local decoded picture generated by the first decoder is stored as a reference picture in the intermediate buffer, and the inter picture decoding by the second decoder is performed by referring the local decoded picture in the intermediate buffer.

Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.

Abstract: An image processing apparatus according to one embodiment determines target resolutions of a plurality of source images based on a first horizontal direction size and a first vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a first display, and a second horizontal direction size and a second vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a second display, and converts the resolution of each of a plurality of source images such that the resolution of each of a plurality of source images becomes the target resolution.

Abstract: A video encoding/decoding system includes a video encoding device and a video decoding device. The video encoding device includes an encoding part for encoding a diagnostic image or normal image. The video decoding device includes a decoding part for decoding the image encoded by the encoding part, a check signal generation part for generating a check signal of the decoded image, a storage part for storing the expected value of the check signal of the diagnostic image or the check signal generated by the check signal generation part, and a comparison part for comparing the check signal stored in the storage part with the check signal generated by the check signal generation part, in order to detect failure in all the paths from the image input part of the video encoding device to the image output part of the video decoding device.

Abstract: The present invention provides a video encoder and a method of operating the video encoder to implement high-precision bit rate control by reducing the risk of overflow of an intermediate buffer coupled between a quantizer and an encoding section. The intermediate buffer supplies a selection control signal indicative of whether the amount of stored data is large or small to a selector. If the selection control signal indicates large, the selector outputs an estimated code amount from a code amount estimation section to the rate controller. If the selection control signal indicates small, the selector outputs an actual code amount from the encoding section to the rate controller. The rate controller calculates the quantization scale according to the output of the selector and feedbacks the calculated quantization scale to the quantizer. The quantizer adjusts the quantizer scale.

Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.

Abstract: An object of the present invention is to detect a failure of a camera input in a system including a camera or a video transmission path (camera input). An image processor includes a hash derivation circuit having a computing unit that calculates hash values on an input screen and a storage circuit that stores the hash values. The image processor compares the hash values between multiple frames so as to decide whether the screens have changed or stopped. A failure is detected when the screens are stopped.

Abstract: In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.

Abstract: The present invention provides a video encoder and a method of operating the video encoder to implement high-precision bit rate control by reducing the risk of overflow of an intermediate buffer coupled between a quantizer and an encoding section. The intermediate buffer supplies a selection control signal indicative of whether the amount of stored data is large or small to a selector. If the selection control signal indicates large, the selector outputs an estimated code amount from a code amount estimation section to the rate controller. If the selection control signal indicates small, the selector outputs an actual code amount from the encoding section to the rate controller. The rate controller calculates the quantization scale according to the output of the selector and feedbacks the calculated quantization scale to the quantizer. The quantizer adjusts the quantizer scale.

Abstract: A display area can be smoothly moved. A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.