Abstract: A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back scheduling thereto.

Abstract: A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back scheduling thereto.

Abstract: A platform configuration measurement device including: a configuration register; means for executing extension processing in which a predetermined operation is performed on a content of the configuration register by using a given additional value, a hash value is obtained by applying a predetermined hash function to a value obtained by the predetermined operation, and the hash value is set for a new content of the configuration register; and measurement extension means for obtaining measured values, corresponding to predetermined components constituting a platform, by sequentially making predetermined measurement on the predetermined components, and for allowing the means for executing extension processing to execute the extension processing using the measured values as the additional values, random extension means is provided for allowing the means for executing extension processing to execute the extension processing using a random value as the additional value.

Abstract: A memory storage system is disclosed. In an exemplary embodiment, the memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements.

Abstract: A security device of this invention includes a nonvolatile storage unit 22 for storing a validity check unit including a counter updated every time signature function means 30 is called up, a volatile storage unit 24 for reading and storing a counter array out of an external nonvolatile storage unit storing the counter array, in which the counter array is obtained by coupling a hash value generated for each signature key with a signature number counter for counting the number of signatures performed by use of the signature key, and a hash function unit 28 for reading the counter array out of the volatile storage unit 24, generating the hash value, and transferring the hash value to the validity check unit for a validity check.

Abstract: To provide an information processing apparatus, a server apparatus, a method of an information processing apparatus, a method of a server apparatus, and an apparatus executable program. An information processing apparatus uses signed integrity values unique to software configuration and asserting integrity of initial codes of a networked server. The server apparatus generates keys used for certifying the server apparatus(S810, S820, S830). One of the keys are certified by a third party to generate a digital signature (S840). The digital signature is attached to the integrity values and the signed integrity values are transmitted to the information processing apparatus for allowing the information processing apparatus to have secure services through the network (S850, S860).

Abstract: A memory storage system is disclosed. In an exemplary embodiment, the memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements.

Abstract: A memory storage system is disclosed. In an exemplary embodiment, the memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements.

Abstract: A carry skip adder has a plurality of ripple adders, in which at least one part of the plurality of ripple adders is divided into a plurality of groups, and a carry signal is transferred from one group to one upper group. In addition, a circuit for calculating C=C2+F*C1 is included, in which the C1 denotes a carry signal from the one group to the one upper group, and the F denotes a signal indicating whether or not outputs of all adders in the one upper group are 1s, and the C2 denotes a carry signal associated with the most upper ripple adder in the one upper group.

Abstract: A memory storage system is disclosed. In an exemplary embodiment, the memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements.

Abstract: An output bit sequences is derived from an initial bit sequence and this output bit sequence is used to encrypt an input bit sequence in a first mode of operation or not to so encrypt the input bit sequence in a second mode of operation. The mode of operation is switched automatically whenever the output bit sequence contains a predetermined trap bit sequence. As a result of this automatic switching between such encryption and no such encryption, unauthorized determination of secret codes is thwarted.

Abstract: A carry skip adder comprises a plurality of ripple adders, wherein at least one part of the plurality of ripple adders is divided into a plurality of groups, and a carry signal is transferred from one group to one upper group. In addition, a circuit for calculating C=C2+F*C1 is included, wherein the C1 denotes a carry signal from the one group to the one upper group, and the F denotes a signal indicating whether or not outputs of all adders in the one upper group are is, and the C2 denotes a carry signal associated with the most upper ripple adder in the one upper group.

Abstract: A data storage system is provided having a faster data transfer rate and reduced complexity though improved control of timing. The data storage system has a plurality of storage devices and a plurality of data buses through which data are transferred. An input/output unit interleaves a plurality of data between an interface and the plurality of data buses while transferring data. A first and a second latch unit, serially connected between the storage devices and the data bus, retain data.

Abstract: The present invention provides a method and apparatus for generating parity in a data storage system. The data storage system includes two or more storage devices having data stored therein, two or more data buses through which the data is transferred, and a selector located between the storage devices and the buses which selectively connects the storage devices and the data buses by a predetermined combination. The selector further includes the capability of calculating parity operations such as an XOR operation. The selector performs the parity operations to logically combine data transferred through the selector between the data buses and the storage devices to produce parity data on the combined data transferred so as to reduce the data transfers over the data bus.

Abstract: A disk storage device includes two data buses 100, 200 for data transfer. Hard disks (HDDs) 0 and 1 are permanently connected to the data buses 100, 200, and hard disks 2 and 3 are selectively connectable to either of the data buses. When a microcontroller (MCU) 32 outputs a specified signal to a data path controller (DPC) 10 in response to a command from a host, multiplexers 20, 22 connect the selectively connectable hard disks 2 and 3 to one of the data buses. When data is written to or read from the hard disks, the write or read can be performed quickly with fewer data buses and a simple device configuration. A parity data generator (PGEN) 24 is connected to both of the buses, receiving new data via one bus and writing new parity data via the other bus.

Abstract: A Unified Memory Architecture (UMA) using intelligent media memory provides an improved way of solving the granularity and memory bandwidth problems in the electronic computer memory system. A specially designed memory chip is attached to an existing attachment point of the system by integrating the bus interface on the memory chip. The memory chip additionally integrates on-chip data-intensive computation functions with the dynamic random access memory (DRAM) macros. Two system attachment points for the new integrated DRAM and logic chip are disclosed; the first using the local central processing unit (CPU) bus interface, and the second using a combination of the main memory bus and an alternative system bus such as a Peripheral Component Interconnect (PCI) bus.

Abstract: An object of the present invention is to provide a data storage system and a parity generation method for the data storage system which make generation of parity easier and which are capable of performing the reconstruction of data at the time of an occurrence of failure with high efficiency and high speed.A data storage system is provided comprising a plurality of devices for storing data, a plurality of data buses for transferring the data, and a selector connected between the plurality of devices and the plurality of data buses for selectively connecting a device and a data bus using a predetermined combination, the selector including a parity operation generator.