Patents by Inventor Seiji Muranaka
Seiji Muranaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220384257Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.Type: ApplicationFiled: August 12, 2022Publication date: December 1, 2022Inventors: Kazuyuki OMORI, Seiji MURANAKA, Kazuyoshi MAEKAWA
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Patent number: 11450561Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.Type: GrantFiled: April 22, 2020Date of Patent: September 20, 2022Assignee: Renesas Electronics CorporationInventors: Kazuyuki Omori, Seiji Muranaka, Kazuyoshi Maekawa
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Publication number: 20200251385Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.Type: ApplicationFiled: April 22, 2020Publication date: August 6, 2020Inventors: Kazuyuki OMORI, Seiji MURANAKA, Kazuyoshi MAEKAWA
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Patent number: 10665502Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.Type: GrantFiled: October 4, 2019Date of Patent: May 26, 2020Assignee: Rensas Electronics CorporationInventors: Kazuyuki Omori, Seiji Muranaka, Kazuyoshi Maekawa
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Publication number: 20200035552Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.Type: ApplicationFiled: October 4, 2019Publication date: January 30, 2020Inventors: Kazuyuki OMORI, Seiji MURANAKA, Kazuyoshi MAEKAWA
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Publication number: 20180240700Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.Type: ApplicationFiled: April 16, 2018Publication date: August 23, 2018Inventors: Kazuyuki OMORI, Seiji MURANAKA, Kazuyoshi MAEKAWA
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Patent number: 9972530Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.Type: GrantFiled: October 20, 2016Date of Patent: May 15, 2018Assignee: Renesas Electronics CorporationInventors: Kazuyuki Omori, Seiji Muranaka, Kazuyoshi Maekawa
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Patent number: 9966455Abstract: The reliability of a semiconductor device is improved. A first gate electrode of a dummy gate electrode including silicon is formed over a semiconductor substrate. Then, by an ion implantation method, a semiconductor region for source or drain of MISFET is formed in the semiconductor substrate. Then, over the semiconductor substrate, an insulation film is formed in such a manner as to cover the first gate electrode. Then, the insulation film is polished to expose the first gate electrode. Then, the surface of the first gate electrode is wet etched by APM. then, the first gate electrode is removed by wet etching using aqueous ammonia. Thereafter, a gate electrode for MISFET is formed in a region from which the first gate electrode has been removed.Type: GrantFiled: July 24, 2017Date of Patent: May 8, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Seiji Muranaka
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Publication number: 20180090597Abstract: The reliability of a semiconductor device is improved. A first gate electrode of a dummy gate electrode including silicon is formed over a semiconductor substrate. Then, by an ion implantation method, a semiconductor region for source or drain of MISFET is formed in the semiconductor substrate. Then, over the semiconductor substrate, an insulation film is formed in such a manner as to cover the first gate electrode. Then, the insulation film is polished to expose the first gate electrode. Then, the surface of the first gate electrode is wet etched by APM. then, the first gate electrode is removed by wet etching using aqueous ammonia. Thereafter, a gate electrode for MISFET is formed in a region from which the first gate electrode has been removed.Type: ApplicationFiled: July 24, 2017Publication date: March 29, 2018Inventor: Seiji MURANAKA
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Patent number: 9576921Abstract: To improve an integration degree of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on the semiconductor substrate, a pad electrode formed on an uppermost wiring layer among the plurality of wiring layers, a base insulating film having a pad opening above the pad electrode, and a rewiring electrically connected to the pad electrode and extending over the base insulating film. Further, the semiconductor device includes a protective film covering an upper surface of the rewiring and having an external pad opening exposing part of the upper surface of the rewiring, an external pad electrode electrically connected to the rewiring through the external pad opening and extending over the protective film, and a wire connected to the external pad electrode. Part of the external pad electrode is located in a region outside the rewiring.Type: GrantFiled: November 25, 2015Date of Patent: February 21, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akira Yajima, Seiji Muranaka
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Publication number: 20170040212Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.Type: ApplicationFiled: October 20, 2016Publication date: February 9, 2017Inventors: Kazuyuki OMORI, Seiji MURANAKA, Kazuyoshi MAEKAWA
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Patent number: 9508646Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.Type: GrantFiled: January 9, 2015Date of Patent: November 29, 2016Assignee: Renesas Electronics CorporationInventors: Kazuyuki Omori, Seiji Muranaka, Kazuyoshi Maekawa
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Patent number: 9508554Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.Type: GrantFiled: September 29, 2015Date of Patent: November 29, 2016Assignee: Renesas Electronics CorporationInventors: Kazuharu Yamabe, Shinichiro Abe, Shoji Yoshida, Hideaki Yamakoshi, Toshio Kudo, Seiji Muranaka, Fukuo Owada, Daisuke Okada
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Publication number: 20160163666Abstract: To improve an integration degree of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on the semiconductor substrate, a pad electrode formed on an uppermost wiring layer among the plurality of wiring layers, a base insulating film having a pad opening above the pad electrode, and a rewiring electrically connected to the pad electrode and extending over the base insulating film. Further, the semiconductor device includes a protective film covering an upper surface of the rewiring and having an external pad opening exposing part of the upper surface of the rewiring, an external pad electrode electrically connected to the rewiring through the external pad opening and extending over the protective film, and a wire connected to the external pad electrode. Part of the external pad electrode is located in a region outside the rewiring.Type: ApplicationFiled: November 25, 2015Publication date: June 9, 2016Inventors: Akira YAJIMA, Seiji MURANAKA
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Publication number: 20160093499Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.Type: ApplicationFiled: September 29, 2015Publication date: March 31, 2016Inventors: Kazuharu YAMABE, Shinichiro ABE, Shoji YOSHIDA, Hideaki YAMAKOSHI, Toshio KUDO, Seiji MURANAKA, Fukuo OWADA, Daisuke OKADA
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Publication number: 20160079188Abstract: Disclosed is a semiconductor device whose reliability can be improved. The semiconductor device includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film.Type: ApplicationFiled: November 25, 2015Publication date: March 17, 2016Inventors: Kazuhito ICHINOSE, Seiji MURANAKA, Kazuyuki OMORI
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Patent number: 9230909Abstract: Disclosed is a semiconductor device whose reliability can be improved. The semiconductor device includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film.Type: GrantFiled: July 29, 2014Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Kazuhito Ichinose, Seiji Muranaka, Kazuyuki Omori
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Publication number: 20150221597Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.Type: ApplicationFiled: January 9, 2015Publication date: August 6, 2015Inventors: Kazuyuki Omori, Seiji Muranaka, Kazuyoshi Maekawa
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Publication number: 20150035156Abstract: Disclosed is a semiconductor device whose reliability can be improved. The semiconductor device includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film.Type: ApplicationFiled: July 29, 2014Publication date: February 5, 2015Inventors: Kazuhito Ichinose, Seiji Muranaka, Kazuyuki Omori
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Publication number: 20110298097Abstract: A semiconductor device is provided wherein stacked semiconductor substrates are electrically coupled together in a satisfactory state by a conductor buried in the interior of a through hole. A first semiconductor substrate includes a substrate having main surfaces, further includes a semiconductor element formed within and over the substrate, a wiring coupled to the semiconductor element electrically, and a conductive layer formed in the interior of a through hole, the through hole extending through mutually confronting first and second main surfaces as the main surfaces of the substrate and reaching the wiring. The first semiconductor substrate and a second semiconductor substrate are stacked and the conductive layer is coupled to a wiring of the second semiconductor substrate electrically. In a second main surface of the conductive layer, a recess is formed around an end portion of the through hole so that a bottom wall surface of the recess is present in the interior of the substrate.Type: ApplicationFiled: June 8, 2011Publication date: December 8, 2011Inventors: Manabu Sueyoshi, Seiji Muranaka, Tomoryo Shono, Itaru Kanno