Patents by Inventor Seiji Muranaka
Seiji Muranaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110254165Abstract: In processes after a TSV is formed, occasionally, cracks appear in an insulation film after the insulation film that is a film for preventing Cu from diffusing is formed and the exposed Cu discolors at a succeeding process of pattern forming such as etching or asking. It is estimated that the problems occur because the volume of Cu expands by heat history at the process of forming a diffusion preventive film. When such film cracking occurs, various problems such as the destruction of the function of a Cu diffusion preventive film and conduction fault with upper wiring caused by the oxidation of Cu at the upper part of a TSV are induced.Type: ApplicationFiled: April 13, 2011Publication date: October 20, 2011Inventor: Seiji MURANAKA
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Publication number: 20110062539Abstract: To provide a semiconductor device in which the deterioration of the rewrite property is suppressed. In a memory cell region, magnetoresistive elements in a semiconductor magnetic-storage device are formed in an array shape in a mode that the magnetoresistive elements are arranged at portions where digit lines extending in one direction intersect bit lines extending in the direction approximately orthogonal to the digit lines. The digit line and the bit line have such a wiring structure constituted by covering a copper film to be a wiring main body with a cladding layer. One end side of the magnetoresistive element is electrically coupled to the bit line via a top via formed from a non-magnetic material.Type: ApplicationFiled: September 17, 2010Publication date: March 17, 2011Inventors: Ryoji MATSUDA, Motoi Ashida, Shuichi Ueno, Shoichi Fukui, Shinya Hirano, Seiji Muranaka, Kazuyuki Omori
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Patent number: 6837963Abstract: A semiconductor device producing method that can clean an edge part of a semiconductor substrate with certainty is provided. The method of producing a semiconductor device includes a step of generating ions and a step of accelerating the ions by means of an electric field and radiating an ion flow onto an edge part of a semiconductor substrate to clean the edge part of the semiconductor substrate. The semiconductor substrate is moved relative to the ion flow while maintaining a state in which the ion flow is being radiated onto the edge part. The step of generating ions includes applying a high-frequency voltage between a pair of electrodes to generate the ions between the electrodes.Type: GrantFiled: October 22, 2001Date of Patent: January 4, 2005Assignees: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Tanaka, Naoki Yokoi, Yasuhiro Asaoka, Seiji Muranaka, Toshihiko Nagai
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Publication number: 20040084316Abstract: It is an object to provide a plating apparatus capable of forming a plated film having a uniform thickness in a substrate to be treated. In a plating apparatus using a face down method in which a voltage is applied between a cathode electrode (5) provided in contact with a peripheral edge portion of a substrate (1) to be treated and an anode electrode (6) provided in a plating solution vessel (3), thereby carrying out plating, there is provided an anode electrode moving device (13) for vertically moving the anode electrode (6) corresponding to a plating situation of the substrate (1).Type: ApplicationFiled: August 26, 2003Publication date: May 6, 2004Applicant: Renesas Technology Corp.Inventor: Seiji Muranaka
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Patent number: 6713232Abstract: Resist residues, which is formed in a process of forming Al interconnections, are removed through use of a single chemical. A chemical which contains an organic acid or a salt thereof and water and which has a pH below 8 is used as a treatment for removing resist or resist residues. The chemical may be used in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching of an Al interconnection; in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching a hole reaching an Al interconnection in an dielectric layer; in a process in which Cu is exposed on the surface of a semiconductor wafer after dry-etching of a Cu interconnection or etching of an interlayer dielectric film laid on a Cu interconnection; and in a process in which metal material such as W, WN, Ti, or TiN; poly-Si; SiN; and SiO2 are exposed on the surface of a wafer after etching of a metal gate.Type: GrantFiled: December 4, 2000Date of Patent: March 30, 2004Assignee: Kao CorporationInventors: Seiji Muranaka, Itaru Kanno, Mami Shirota, Junji Kondo
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Patent number: 6642142Abstract: In a water rinsing process performed after the surface of a substrate has been cleaned using a cleaning solution, a first spinning process, in which water is supplied to the surface of the substrate while the substrate is rotated at a first rotation speed, and a second spinning process, in which the substrate is rotated at a second rotation speed that is higher than the first rotation speed, are repeatedly performed alternately.Type: GrantFiled: January 3, 2002Date of Patent: November 4, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshihiko Nagai, Hiroshi Tanaka, Naoki Yokoi, Yasuhiro Asaoka, Seiji Muranaka
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Publication number: 20030139046Abstract: Disclosed is a method for removing Pt (or Pt—Ir) and BST contaminants on the surface edge, back, and bevel of a semiconductor wafer. A wafer on which a stacked film selected from the group of a Pt film, a Pt—Ir film, and a Ba—Sr—Ti film is formed is prepared. A chemical containing hydrochloric acid is applied only to the surface edge, back, and bevel of the wafer. The surface edge, back, and bevel of the wafer are rinsed with pure water. Further, a chemical containing hydrogen fluoride is applied. The surface edge, back, and bevel of the wafer are rinsed again with pure water.Type: ApplicationFiled: February 27, 2003Publication date: July 24, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yasuhiro Asaoka, Hiroshi Tanaka, Naoki Yokoi, Seiji Muranaka, Toshihiko Nagai
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Patent number: 6586145Abstract: A method of fabricating a semiconductor device causing no pattern shifting of a peripheral oxide film etc. in removal of both of an antireflection film and a mask pattern and having a fine structure not implementable solely by photolithography and the semiconductor device are obtained. The method of fabricating a semiconductor device comprises steps of forming a base film of either a silicon film or a silicon compound film on a semiconductor substrate, forming a hard film of either a metal film or a metal compound film on the base film, forming a resist pattern on the hard film, dryly etching the hard film through the resist pattern serving as a mask for forming a hard pattern, dryly etching the base film through the hard pattern serving as a mask and removing the hard pattern by wet etching with a chemical solution not etching at least the base film.Type: GrantFiled: February 13, 2002Date of Patent: July 1, 2003Assignees: Mitsubishi Denki Kabushiki Kaisha, Matsushita Electric Industrial Co., Ltd.Inventors: Naoki Yokoi, Hiroshi Tanaka, Yasuhiro Asaoka, Seiji Muranaka, Toshihiko Nagai
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Publication number: 20030119331Abstract: In the method for removing etching residue adhered on a semiconductor substrate using a stripping liquid containing fluorine, the stripping liquid on the semiconductor substrate can be flung away by rotating the semiconductor substrate after the residue removing treatment. Thereby, the etching of the interlayer insulating film caused between the residue removing treatment and washing with water can be minimized.Type: ApplicationFiled: May 21, 2002Publication date: June 26, 2003Inventor: Seiji Muranaka
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Patent number: 6531381Abstract: Disclosed is a method for removing Pt (or Pt—Ir) and BST contaminants on the surface edge, back, and bevel of a semiconductor wafer. A wafer on which a stacked film selected from the group of a Pt film, a Pt—Ir film, and a Ba—Sr—Ti film is formed is prepared. A chemical containing hydrochloric acid is applied only to the surface edge, back, and bevel of the wafer. The surface edge, back, and bevel of the wafer are rinsed with pure water. Further, a chemical containing hydrogen fluoride is applied. The surface edge, back, and bevel of the wafer are rinsed again with pure water.Type: GrantFiled: December 3, 2001Date of Patent: March 11, 2003Assignees: Mitsubishi Denki Kabushiki Kaisha, Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Asaoka, Hiroshi Tanaka, Naoki Yokoi, Seiji Muranaka, Toshihiko Nagai
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Publication number: 20030003754Abstract: A method of fabricating a semiconductor device causing no pattern shifting of a peripheral oxide film etc. in removal of both of an antireflection film and a mask pattern and having a fine structure not implementable solely by photolithography and the semiconductor device are obtained. The method of fabricating a semiconductor device comprises steps of forming a base film of either a silicon film or a silicon compound film on a semiconductor substrate, forming a hard film of either a metal film or a metal compound film on the base film, forming a resist pattern on the hard film, dryly etching the hard film through the resist pattern serving as a mask for forming a hard pattern, dryly etching the base film through the hard pattern serving as a mask and removing the hard pattern by wet etching with a chemical solution not etching at least the base film.Type: ApplicationFiled: February 13, 2002Publication date: January 2, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Naoki Yokoi, Hiroshi Tanaka, Yasuhiro Asaoka, Seiji Muranaka, Toshihiko Nagai
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Publication number: 20020197853Abstract: In a water rinsing process performed after the surface of a substrate has been cleaned using a cleaning solution, a first spinning process, in which water is supplied to the surface of the substrate while the substrate is rotated at a first rotation speed, and a second spinning process, in which the substrate is rotated at a second rotation speed that is higher than the first rotation speed, are repeatedly performed alternately.Type: ApplicationFiled: January 3, 2002Publication date: December 26, 2002Inventors: Toshihiko Nagai, Hiroshi Tanaka, Naoki Yokoi, Yasuhiro Asaoka, Seiji Muranaka
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Publication number: 20020177310Abstract: Disclosed is a method for removing Pt (or Pt—Ir) and BST contaminants on the surface edge, back, and bevel of a semiconductor wafer. A wafer on which a stacked film selected from the group of a Pt film, a Pt—Ir film, and a Ba—Sr—Ti film is formed is prepared. A chemical containing hydrochloric acid is applied only to the surface edge, back, and bevel of the wafer. The surface edge, back, and bevel of the wafer are rinsed with pure water. Further, a chemical containing hydrogen fluoride is applied. The surface edge, back, and bevel of the wafer are rinsed again with pure water.Type: ApplicationFiled: December 3, 2001Publication date: November 28, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yasuhiro Asaoka, Hiroshi Tanaka, Naoki Yokoi, Seiji Muranaka, Toshihiko Nagai
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Publication number: 20020168879Abstract: A semiconductor device producing method that can clean an edge part of a semiconductor substrate with certainty is provided. The method of producing a semiconductor device includes a step of generating ions and a step of accelerating the ions by means of an electric field and radiating an ion flow onto an edge part of a semiconductor substrate to clean the edge part of the semiconductor substrate. The semiconductor substrate is moved relative to the ion flow while maintaining a state in which the ion flow is being radiated onto the edge part. The step of generating ions includes applying a high-frequency voltage between a pair of electrodes to generate the ions between the electrodes.Type: ApplicationFiled: October 22, 2001Publication date: November 14, 2002Applicant: Mitsubishi Denki Kabushiki Kaisha and Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Tanaka, Naoki Yokoi, Yasuhiro Asaoka, Seiji Muranaka, Toshihiko Nagai
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Publication number: 20020146911Abstract: A method of manufacturing a semiconductor device, having a resist-removing step which is improved so as not to etch a peripheral material and damage the peripheral material is provided. A resist pattern is formed on a substrate. Using the resist pattern as a mask, the substrate is etched. A surface-deteriorated layer of the resist pattern is removed by a first chemicals treatment. A bulk portion of the resist pattern is removed by a second chemicals treatment.Type: ApplicationFiled: September 26, 2001Publication date: October 10, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Seiji Muranaka, Hiroshi Tanaka, Naoki Yokoi, Yasuhiro Asaoka, Toshihiko Nagai
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Patent number: 6410454Abstract: In a semiconductor wafer-processing, hydrogen gas is introduced into the same chamber as used for film formation and heated to generate hydrogen radicals. Alternatively, a plasma is applied to generate hydrogen radicals, or the semiconductor wafer is heated immediately before film formation. Thereby, contaminants on the surface of the wafer are removed. Thereafter, a conductive film or an insulating film is formed on the wafer in the same chamber.Type: GrantFiled: December 2, 1997Date of Patent: June 25, 2002Assignee: Mitsubishi Denki KabushikiInventors: Seiji Muranaka, Cozy Ban, Akihiko Osaki
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Patent number: 6358329Abstract: The resist residue removal method removes resist residues caused at the time of formation of an aluminum wiring pattern on a semiconductor wafer. The method includes the steps of removal fluid processing, washing, and drying. The method involves forming an atmosphere within a chamber, which houses a semiconductor wafer having an exposed aluminum wiring pattern, by controlling gas flow into the chamber according to the processing step being performed. By the resist residue removal method, yield of a wiring pattern is improved by prevention of local etching of an aluminum wiring pattern, or by prevention of thinning of the aluminum wiring pattern.Type: GrantFiled: June 29, 1999Date of Patent: March 19, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Seiji Muranaka, Itaru Kanno
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Publication number: 20020012882Abstract: Resist residues, which is formed in a process of forming Al interconnections, are removed through use of a single chemical. A chemical which contains an organic acid or a salt thereof and water and which has a pH below 8 is used as a treatment for removing resist or resist residues. The chemical may be used in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching of an Al interconnection; in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching a hole reaching an Al interconnection in an dielectric layer; in a process in which Cu is exposed on the surface of a semiconductor wafer after dry-etching of a Cu interconnection or etching of an interlayer dielectric film laid on a Cu interconnection; and in a process in which metal material such as W, WN, Ti, or TiN; poly-Si; SiN; and SiO2 are exposed on the surface of a wafer after etching of a metal gate.Type: ApplicationFiled: December 4, 2000Publication date: January 31, 2002Applicant: Mitsubishi Denki Kabushiki Kaisha and Kao CorporationInventors: Seiji Muranaka, Itaru Kanno, Mami Shirota, Junji Kondo
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Patent number: 6340253Abstract: A resist peeling system includes a peeling solution tank for storing a resist peeling solution; an electric conductivity monitor for monitoring the electric conductivity of a resist peeling solution; and a additive components tank for estimating the components ratio in the resist peeling solution on the basis of the electric conductivity thereof and adding, when a component of the resist peeling solution is estimated to be insufficient on the basis of the estimated result, the component lacking for the resist peeling solution to the resist peeling solution by a suitable amount.Type: GrantFiled: July 5, 2000Date of Patent: January 22, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Seiji Muranaka, Hiroshi Tanaka, Yoshiyuki Hori
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Patent number: 6053059Abstract: An organic substance analyzing system identifies and quantifies organic substances adhering to the surface of a sample placed in a chamber for a local organic substance analysis on the surface of the sample. The organic substance analyzing system heats a portion of the sample from the front side or the back side of the sample, collects gases discharged out of the portion of the surface and analyzes the collected gases. A lamp, a laser or an electron beam source is used as a heating means for locally heating a portion to be analyzed on the surface of the sample to locally discharge the gases out of the portion. Otherwise, the entire surface of the sample is heated, and the discharged gases are collected for every section so as to be analyzed.Type: GrantFiled: June 3, 1998Date of Patent: April 25, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Seiji Muranaka, Kuniaki Miyake