Abstract: An airbag module installation system includes an airbag module with an airbag and a case configured to hold the airbag module prior to and during installation of the airbag module into a vehicle. The installation system may include a “one-touch” clip configured to fasten the airbag module to a vehicle body. The installation system can be permanently fastened to the vehicle body and control deployment direction of an airbag. The installation system can also provide temporary fixing of the airbag module to a vehicle body.

Abstract: A curtain airbag bracket mounts a curtain airbag having an attachment piece provided in an edge portion of the curtain airbag to a vehicle body. The curtain airbag bracket includes a vehicle body attaching portion for attaching the curtain airbag bracket to the vehicle body, and an airbag mounting portion for mounting the attachment piece. The airbag mounting portion has a bent portion or a curved portion extending from the vehicle body attaching portion toward an inside of the vehicle body.

Abstract: A multi-phase oscillator includes a plurality of ring oscillators (21) each having a plurality of output ports and each formed by connecting an odd number of inverters (20) in a ring, and a plurality of resistance elements (30) coupling the output ports between the plurality of ring oscillators (21) so that all of the plurality of ring oscillators (21) operate at an identical frequency while keeping a desired phase relationship. The number of the ring oscillators (21) is not limited to an odd number but may be an even number. The multi-phase oscillator changes the state of a succeeding node of a phase coupling to accord with the state of a preceding node of the phase coupling by using the resistance elements (30) as phase coupling devices. If resistors are used as the resistance elements (30), the phase output accuracy greatly improves and high frequency oscillation is possible.

Abstract: This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

Abstract: In a control operation performed at the time of earthquake or strong wind, when a running elevator is stopped at the nearest floor, the natural frequency of the transverse vibration of a rope is prevented from resonating with the natural frequency of the building, and thereby the increase in transverse vibration of the rope is restrained. There is provided a rope resonance checking means in which, in the control operation in which when a shake of the building caused by earthquake or strong wind is detected, a running elevator is stopped at the nearest floor, or an elevator passing through an express zone is stopped emergently and runs at a low speed to the nearest floor, the natural frequency of the transverse vibration of the rope is compared with the natural frequency of the building, and selects the car stop position at a non-resonance position so as to prevent the natural frequency of the transverse vibration of the rope from resonating with the natural frequency of the building.

Abstract: This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

Abstract: A substrate processing apparatus comprises a reaction chamber which is to accommodate stacked substrates, a gas introducing portion, and a buffer chamber, wherein the gas introducing portion is provided along a stacking direction of the substrates, and introduces substrate processing gas into the buffer chamber, the buffer chamber includes a plurality of gas-supply openings provided along the stacking direction of the substrates, and the processing gas introduced from the gas introducing portion is supplied from the gas-supply openings to the reaction chamber.

Abstract: A substrate processing apparatus comprises a reaction chamber which is to accommodate stacked substrates, a gas introducing portion, and a buffer chamber, wherein the gas introducing portion is provided along a stacking direction of the substrates, and introduces substrate processing gas into the buffer chamber, the buffer chamber includes a plurality of gas-supply openings provided along the stacking direction of the substrates, and the processing gas introduced from the gas introducing portion is supplied from the gas-supply openings to the reaction chamber.

Abstract: In a voltage controlled oscillation circuit including a cascade connection of a voltage-to-current conversion circuit (310) for generating an input voltage converted current which is a current corresponding to an input voltage and a current controlled oscillation circuit (120) of which an oscillation frequency varies according to the input voltage converted current, the voltage-to-current conversion circuit (310) includes a first current source for outputting a current in proportion to the input voltage and a plurality of second current sources for outputting a current in proportion to a voltage obtained by shifting the input voltage. Then, a current obtained by adding a current output from the first current source and currents output from the plurality of current sources is output as the input voltage converted current to the current controlled oscillation circuit (120).

Abstract: A semiconductor integrated circuit having jitter measuring function includes a slicer (11), a T/V converter (12), an A/D converter (13), a processor (14), a multiplexer (15), and a correction section (16). The slicer (11) binarizes an input signal to generate a data signal. The T/V converter (12) outputs a voltage corresponding to the data length of an input signal. The multiplexer (15) selects the data signal or a reference signal as the input signal to the T/V converter (12). The A/D converter (13) converts the output voltage of the TN converter (12) to digital data. The processor (14) measures jitter in the input signal to the T/V converter (12) in accordance with the digital data. The correction section (16) compares the output voltage of the T/V converter (12) produced where the reference signal has been selected by the multiplexer (15) with a predetermined voltage, and corrects the output characteristics of the T/V converter (12) according to the comparison results.

Abstract: A substrate processing apparatus comprises a reaction chamber which is to accommodate stacked substrates, a gas introducing portion, and a buffer chamber, wherein the gas introducing portion is provided along a stacking direction of the substrates, and introduces substrate processing gas into the buffer chamber, the buffer chamber includes a plurality of gas-supply openings provided along the stacking direction of the substrates, and the processing gas introduced from the gas introducing portion is supplied from the gas-supply openings to the reaction chamber.

Abstract: This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

Abstract: A system for designing connecting terminals of a semiconductor device, having a power supply cell arranging unit configured to arrange power supply cells at some of I/O slots formed in a semiconductor chip, an I/O signal cell arranging unit configured to arrange I/O signal cells at some of the I/O slots where the power supply cells are not arranged, a first connecting net generator configured to generate a first connecting net connecting the I/O slots to bumps formed on the semiconductor chip, a second connecting net generator configured to generate a second connecting net connecting the bumps to external electrodes formed on a package base, and a verifier configured to verify whether the power supply cells, I/O signal cells, and first and second connecting nets violate predetermined design rules.

Abstract: This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

Abstract: A system for designing connecting terminals of a semiconductor device, having a power supply cell arranging unit configured to arrange power supply cells at some of I/O slots formed in a semiconductor chip, an I/O signal cell arranging unit configured to arrange I/O signal cells at some of the I/O slots where the power supply cells are not arranged, a first connecting net generator configured to generate a first connecting net connecting the I/O slots to bumps formed on the semiconductor chip, a second connecting net generator configured to generate a second connecting net connecting the bumps to external electrodes formed on a package base, and a verifier configured to verify whether the power supply cells, I/O signal cells, and first and second connecting nets violate predetermined design rules.

Abstract: A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.

Abstract: An airbag module installation system includes an airbag module with an airbag and a case configured to hold the airbag module prior to and during installation of the airbag module into a vehicle. The installation system may include a “one-touch” clip configured to fasten the airbag module to a vehicle body. The installation system can be permanently fastened to the vehicle body and control deployment direction of an airbag. The installation system can also provide temporary fixing of the airbag module to a vehicle body.

Abstract: This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

Abstract: A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data pulse and the VCO clock; a selector for selectively outputting a signal supplied from the frequency comparator; a first charge pump for increasing/decreasing the output voltage on the basis of the output from the selector; a second charge pump for increasing/decreasing the output voltage on the basis of the output from the phase comparator; a loop filter for eliminating unnecessary components included in a signal obtained by adding the output from the first charge pump and the output from the second charge pump; and a VCO for generating a clock of a frequency corresponding to the output voltage of the loop filter.

Abstract: A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data pulse and the VCO clock; a selector for selectively outputting a signal supplied from the frequency comparator, a first charge pump for increasing/decreasing the output voltage on the basis of the output from the selector; a second charge pump for increasing/decreasing the output voltage on the basis of the output from the phase comparator; a loop filter for eliminating unnecessary components included in a signal obtained by adding the output from the first charge pump and the output from the second charge pump; and a VCO for generating a clock of a frequency corresponding to the output voltage of the loop filter.