Patents by Inventor Seiji Yamada

Seiji Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12015864
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: June 18, 2024
    Assignee: Sony Group Corporation
    Inventors: Masaki Sakakibara, Kenichi Aoyagi, Seiji Yamada
  • Patent number: 11996794
    Abstract: A motor control device controls a drive of a motor having a coil, and includes a drive circuit and a control unit. The drive circuit has a plurality of switching elements, and switches the energization of the coil. The control unit includes an energization control part and a current limit part. The energization control part accelerates and then decelerates the motor, and controls energization of the coil so that a rotation position of the motor stops at a target rotation position. The current limit part limits the current during a deceleration control.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: May 28, 2024
    Assignee: DENSO CORPORATION
    Inventors: Jun Yamada, Seiji Nakayama, Kouji Sakaguchi, Haruka Miyano
  • Publication number: 20240128362
    Abstract: Provided is a semiconductor device comprising: a plurality of trench portions include a gate trench portion and a dummy trench portion; a first lower end region of a second conductivity type that is provided to be in contact with lower ends of two or more trench portions which include the gate trench portion; a well region of a second conductivity type that is arranged in a different location from the first lower end region in a top view, and a second lower end region of a second conductivity type that is provided between the first lower end region and the well region in a top view being separated from the first lower end region and the well region, and provided to be in contact with lower ends of one or more trench portions including the gate trench portion.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 18, 2024
    Inventors: Yosuke SAKURAI, Seiji NOGUCHI, Kosuke YOSHIDA, Ryutaro HAMASAKI, Takuya YAMADA
  • Publication number: 20240120413
    Abstract: Provided is a semiconductor device comprising: a plurality of trench portions; a first lower end region of a second conductivity type that is provided to be in contact with lower ends of two or more trench portions which include the gate trench portion; a well region of the second conductivity type that is arranged in a different location from the first lower end region in a top view, and a second lower end region of the second conductivity type that is provided between the first lower end region and the well region in a top view being separated from the first lower end region and the well region, and provided to be in contact with lower ends of one or more trench portions including the gate trench portion.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: Yosuke SAKURAI, Seiji NOGUCHI, Kosuke YOSHIDA, Ryutaro HAMASAKI, Takuya YAMADA
  • Publication number: 20240072110
    Abstract: Provided is a semiconductor device including a transistor portion, in which the transistor portion has a drift region of a first conductivity type provided in a semiconductor substrate, a base region of a second conductivity type provided above the drift region, an accumulation region of the first conductivity type provided above the drift region, a plurality of trench portions provided to extend from a front surface of the semiconductor substrate to the drift region, and a trench bottom portion of the second conductivity type provided in bottom portions of the plurality of trench portions, and the accumulation region has a doping concentration with a half width of 0.3 ?m or more.
    Type: Application
    Filed: July 24, 2023
    Publication date: February 29, 2024
    Inventors: Nao SUGANUMA, Yosuke SAKURAI, Seiji NOGUCHI, Ryutaro HAMASAKI, Takuya YAMADA
  • Publication number: 20230362514
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 9, 2023
    Applicant: SONY GROUP CORPORATION
    Inventors: Masaki SAKAKIBARA, Kenichi AOYAGI, Seiji YAMADA
  • Patent number: 11758305
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: September 12, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Masaki Sakakibara, Kenichi Aoyagi, Seiji Yamada
  • Publication number: 20220329748
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.
    Type: Application
    Filed: June 13, 2022
    Publication date: October 13, 2022
    Applicant: SONY CORPORATION
    Inventors: Masaki SAKAKIBARA, Kenichi AOYAGI, Seiji YAMADA
  • Patent number: 11394912
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: July 19, 2022
    Assignee: SONY CORPORATION
    Inventors: Masaki Sakakibara, Kenichi Aoyagi, Seiji Yamada
  • Patent number: 10944932
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 9, 2021
    Assignee: Sony Corporation
    Inventors: Masaki Sakakibara, Kenichi Aoyagi, Seiji Yamada
  • Patent number: 10920821
    Abstract: [Problem] To provide a terminal securing device the size of which can be reduced. [Solution] When a key lock 7 is positioned in a second position a key 6 and the key lock 7 are arranged at overlapping positions in the lengthwise direction of a rod 3, so a portion of a space for displacing the key lock 7 from the second position to a first position can be provided at a position overlapping the key 6 in the lengthwise direction of the rod 3. Thus, an increase in the size of a holder 4 in the lengthwise direction of the rod 3 can be avoided, so the size of the terminal securing device 1 can be reduced.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: February 16, 2021
    Assignee: CHUO HATSUJO KABUSHIKI KAISHA
    Inventors: Kenta Imai, Shinji Okamoto, Seiji Yamada
  • Publication number: 20200389615
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.
    Type: Application
    Filed: August 21, 2020
    Publication date: December 10, 2020
    Applicant: SONY CORPORATION
    Inventors: Masaki SAKAKIBARA, Kenichi AOYAGI, Seiji YAMADA
  • Patent number: 10855910
    Abstract: An electronic device according to a first aspect comprises an imaging device and a processor. The imaging device has a predetermined imaging region, and is configured to capture images having different focal distances. The processor is configured to execute a first process of identifying two or more focus identification regions included in a first imaging region included in the predetermined imaging region by comparing the captured images in the first imaging region, and a second process of interpolating a focal distance of a middle region not belonging to the two or more focus identification regions in the first imaging region. The second process includes a process of interpolating the focal distance of the middle region based on a focal distance of an interpolation focus region that is located inside or outside the middle region and that is one of the two or more focus identification regions.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: December 1, 2020
    Assignee: KYOCERA Corporation
    Inventors: Masaki Tano, Masayoshi Kondo, Yusuke Suzuki, Masaya Kawakita, Seiji Yamada, Tomohiro Hamaguchi, Koji Saijo
  • Publication number: 20200277983
    Abstract: [Problem] To provide a terminal securing device the size of which can be reduced. [Solution] When a key lock 7 is positioned in a second position a key 6 and the key lock 7 are arranged at overlapping positions in the lengthwise direction of a rod 3, so a portion of a space for displacing the key lock 7 from the second position to a first position can be provided at a position overlapping the key 6 in the lengthwise direction of the rod 3. Thus, an increase in the size of a holder 4 in the lengthwise direction of the rod 3 can be avoided, so the size of the terminal securing device 1 can be reduced.
    Type: Application
    Filed: July 24, 2018
    Publication date: September 3, 2020
    Inventors: Kenta Imai, Shinji Okamoto, Seiji Yamada
  • Publication number: 20200068134
    Abstract: An electronic device according to a first aspect comprises an imaging device and a processor. The imaging device has a predetermined imaging region, and is configured to capture images having different focal distances. The processor is configured to execute a first process of identifying two or more focus identification regions included in a first imaging region included in the predetermined imaging region by comparing the captured images in the first imaging region, and a second process of interpolating a focal distance of a middle region not belonging to the two or more focus identification regions in the first imaging region. The second process includes a process of interpolating the focal distance of the middle region based on a focal distance of an interpolation focus region that is located inside or outside the middle region and that is one of the two or more focus identification regions.
    Type: Application
    Filed: August 26, 2019
    Publication date: February 27, 2020
    Applicant: KYOCERA Corporation
    Inventors: Masaki TANO, Masayoshi KONDO, Yusuke SUZUKI, Masaya KAWAKITA, Seiji YAMADA, Tomohiro HAMAGUCHI, Koji SAIJO
  • Publication number: 20190313045
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Applicant: SONY CORPORATION
    Inventors: Masaki SAKAKIBARA, Kenichi AOYAGI, Seiji YAMADA
  • Patent number: 10348992
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 9, 2019
    Assignee: Sony Corporation
    Inventors: Masaki Sakakibara, Kenichi Aoyagi, Seiji Yamada
  • Patent number: 10281400
    Abstract: A method for enhancing luminescence of a luminous material, a substance detection method, a substance detection apparatus, and a luminescence enhancer are provided. A method for enhancing luminescence of a luminous material, the method including: holding, in a luminescence detection unit, the luminous material and a white colloidal particle both contained in a liquid; and irradiating the luminescence detection unit with light, in which the luminescence detection unit has an inner diameter of 300 ?m or less in an optical axis direction.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: May 7, 2019
    Assignee: SONY CORPORATION
    Inventors: Shuji Fujita, Kyohei Yoshimitsu, Seiji Yamada, Daisuke Yamaguchi, Yoshio Goto
  • Publication number: 20180241960
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.
    Type: Application
    Filed: April 24, 2018
    Publication date: August 23, 2018
    Applicant: SONY CORPORATION
    Inventors: Masaki SAKAKIBARA, Kenichi AOYAGI, Seiji YAMADA
  • Patent number: 10048845
    Abstract: A mobile electronic apparatus comprises a display including a display area having a first edge and a second edge, an input unit including a detector, and at least one processor. The display displays a display screen on the display area. The detector detects an operation performed on the display area. The at least one processor places a mode change element adjacent to the first edge or the second edge of the display area, scales down the display screen in response to detection of a first operation performed on the mode change element, and displays the display screen, which is scaled down, as a scaled-down screen on a part of the display area. The at least one processor determines, in response to a user's input to the input unit, which one of the first edge and the second edge is to be adjacent to the mode change element.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: August 14, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Seiji Yamada, Natsuhito Honda