Abstract: A push-pull type control cable having a conduit tube and an inner cable comprised of a core wire and a plurality of strands wound around the core wire and inserted into the conduit tube, the control cable being filled with lubricant at a clearance between an inner periphery of the conduit tube and an outer periphery of the inner cable, wherein the plurality of strands each are comprised of three pieces of twisted element wires.

Abstract: Memory cells each having a floating gate (4), control gate (6), and source and drain diffusion layers (7a, 7b) are formed on a silicon substrate (1). A silicon nitride film (10) by low-pressure CVD is maintained as side wall insulating films on side walls of the gates in each memory cell. A silicon nitride film (11) by plasma CVD is formed to cover a memory cell array, and silicon oxide films (12a, 12b) are made on the silicon nitride film (11) to forman inter-layer insulating film. Acommon source line (13) connected to the source diffusion layer 7a is formed to embed in the silicon oxide film (12a), and a bit line (14) connected to the drain diffusion layer (7b) is formed on the silicon oxide film (12b).

Abstract: A pattern constituted of a main bit line and four sub-bit lines is repeated around a column sub-selector of the flash EEPROM employing a double bit architecture having four block selection transistors per pitch of the pattern. In the flash EEPROM having a memory cell array and a column selector divided into a plurality of cell blocks 11i and a plurality of column sub selectors 12i, respectively, the column sub-selector including repeated patterns each having four sub bit lines (SBLs) and a single main bit line (MBL) arranged in a column direction. In a pitch of the repeating pattern, active regions for four block selection transistors (BSTs) are arranged. Gate wiring layers of each of the block selection transistors are arranged above the active region in a row direction and four block decode lines (BDLi) are arranged above the active region in the row direction.

Abstract: A push-pull type control cable having a conduit tube and an inner cable comprised of a core wire and a plurality of strands wound around the core wire and inserted into the conduit tube, the control cable being filled with lubricant at a clearance between an inner periphery of the conduit tube and an outer periphery of the inner cable, wherein the plurality of strands each are comprised of three pieces of twisted element wires.

Abstract: A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines.

Abstract: A push-pull type control cable having a conduit tube and an inner cable comprised of a core wire and a plurality of strands wound around the core wire and inserted into the conduit tube, the control cable being filled with lubricant at a clearance between an inner periphery of the conduit tube and an outer periphery of the inner cable, wherein the plurality of strands each are comprised of three pieces of twisted element wires.

Abstract: A heavy duty pneumatic radial tire comprises a radial carcass, a main cross belt and a tread portion, in which the main cross belt is formed by laminating at least three rubberized cord layers so that the cords in each layer are parallel to each other but the cords between the adjoining layers are crossed with each other and extend in opposite directions with respect to an equatorial line of the tire. In such a tire, a pair of cushion rubbers are arranged between the adjoining rubberized cord layers constituting the main cross belt at their both end portions by setting a position relation between mutual cushion rubbers at both belt ends to an optimum value to thereby prevent or control the occurrence of the belt end separation failure.

Abstract: A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines.

Abstract: According to a method for screening a nonvolatile semiconductor memory device, data is written to all memory cells. The data is slightly erased such that the memory cells have a positive distribution of threshold voltages. The threshold voltages of the memory cells are measured, and the number of memory cells whose threshold voltages are lower than a reference threshold voltage, is counted. When the counted number is not larger than the number of spare cells provided in a redundant circuit, the memory cells whose threshold voltages are lower than the reference threshold voltage are replaced with the spare cells. When the counted number is larger than the number of spare cells, the nonvolatile semiconductor memory device is determined as a defective one.

Abstract: In this invention, charges are extracted from the charge storage portion by means of F-N tunnel current, and then avalanche hot carriers are injected into the storage portion.

Abstract: Here is disclosed a controller for operation of transmission in motor car comprising a control cable (14) of triple structure consisting of an outer tube (15), an inner tube (16) slidably inserted into the outer tube (15) and a length of wire (17) slidably inserted into the inner tube (16), characterized by that any one end of the outer tube (15) is fixed to a car body, one end of any one of the inner tube (16) and the wire (17) is engaged with a SELECT mode operating mechanism provided adjacent a control lever (6) while one end of the other one of the inner tube (16) and the wire (17) is engaged with a SHIFT mode operating mechanism also provided adjacent the control lever (6), the other end of the outer tube (15) is fixed to a transmission casing, the other end of any one of the inner tube (16) and the wire (17) is engaged with a SELECT mode operating mechanism provided adjacent a transmission unit while the other end of the other one of the inner tube (16) and the wire (17) is engaged with a SHIFT mode ope

Abstract: In this invention, charges are extracted from the charge storage portion by means of F-N tunnel current, and then avalanche hot carriers are injected into the storage portion.

Abstract: A non-volatile semiconductor memory cell has a channel layer with a two-layered structure including a surface channel layer and a buried channel layer. The operation of reading out "1" level data or "0" level data from the memory cell is effected by using only the buried channel layer and based on whether the conductivity type of the buried layer is inverted or not. The operation of writing "0" level data is effected by using both of the surface channel layer and the buried channel layer, simultaneously inverting the conductivity types of the surface channel layer and the buried channel layer, and passing a current into the inverted layer to generate hot electrons.

Abstract: In this invention, charges are extracted from the charge storage portion by means of F-N tunnel current, and then avalanche hot carriers are injected into the storage portion.

Abstract: A method for manufacturing a floating gate field effect transistor includes the steps of forming a plurality of first band-like insulating films over a semiconductor substrate in a parallel, spaced-apart relation and a second insulating film between the first insulating films and having a thickness smaller than that of the first insulating film, forming a plurality of first conductive layers selectively over the insulating layer and a plurality of second band-like conductive layers over the first conductive layers in a spaced-apart relation and in a direction perpendicular to the first and second insulating films, the first conductive layer having a width substantially the same as that of the second conductive layer, coating a first resist over a whole surface of a resultant structure and patterning it so as to protect a substantive source region, removing the first insulating film at those areas not covered by the first resist, removing the first resist, forming a third insulating film by a thermal oxidation

Abstract: A method of this invention is applied to a nonvolatile memory device composed of first memory cells connected to one of a first word-line pair and second memory cells connected to the other of the first word-line pair, and a single source shared by the first memory cells and the second memory cells. First, a positive potential of, for example, 5 V is applied to the source, a negative potential of, for example, -10 V is applied to the one of the word-line pair, and the ground potential to the other of the word-line pair. This permits electrons to move from the floating gate of the first memory cells into the source, with the result that the erasing of information is achieved. Next, the positive potential is applied to the source, the negative potential is applied to the other of the word-line pair, and the ground potential to the one of the word-line pair.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array including memory cell transistors having a lamination gate structure are arranged in a matrix manner at the position where a word line and a bit line cross each other. A lower voltage than a threshold voltage is applied to the word line selected at the time of a reading mode in a state that no electrical charge is stored in the floating gate.

Abstract: The present invention provides a method of manufacturing a nonvolatile semiconductor memory device. In the method of the present invention. Arsenic ions are implanted into an element region of a silicon substrate so as to form a first impurity region. Then, an insulating film is formed on the silicon substrate in the element region, followed by forming a heat resistant film on the entire surface of the silicon substrate. Further, a resist film is formed on the silicon substrate, followed by patterning the resist film to form an opening on at least the first impurity region. After the patterning step, the heat resistant film positioned below the opening of the resist film is removed, followed by implanting phosphorus ions into the substrate using the patterned resist film as a mask so as to form a second impurity region. In the next step, the resist film is removed and, then, annealing is applied with the heat resistant film used as a mask.

Abstract: For a system such as a combinational weighing system that requires a large number of parameters to be set for its operation, groups of parameters which frequently assume same sets of values are identified and each of such sets is assigned a reservation number. Memory space for storing values assumed by the parameters can be reduced if these values are grouped by such frequently occurring combinations and the user specifies a single reservation number instead of specifying values of the individual parameters. Selection of operating condition is effected by an input device with a touch screen. For some parameters, currently set values are displayed as a bar graph and a user can set or reset a value directly on the screen by moving a cursor on the bar graph.

Abstract: In a method of applying a voltage pulse for injecting/extracting electrons into/from a non-volatile semiconductor memory in which high and low levels of a threshold voltage corresponding to presence and absence of storage of electrons are caused to correspond to binary information, the method includes the steps of generating a plurality of voltage pulses each having an ability of injecting or extracting only a portion of all electrons to be stored, and applying the plurality of voltage pulses to the non-volatile semiconductor memory to thereby carry out injection/extraction of all the electrons.