Abstract: A thin-film capacitor structure (50) is joined to an electrode pad surface (2S) of an area array integrated circuit (2) having a plurality of electrode pads (3G, 3P, 3S) arranged in an area array on the electrode pad surface (2S). The thin-film capacitor structure (50) includes a thin-film capacitor (10) including a first sheet electrode (11), a second sheet electrode (13), and a thin-film dielectric layer (12) formed between the first sheet electrode (11) and the second sheet electrode (12), a first insulating film (21), a second insulating film (22), and a plurality of through holes (30P, 30G, 30S). The plurality of through holes (30P, 30G, 30S) are bored from the first insulating film (21) to the second insulating film (22) through the thin-film capacitor (10) and formed in positions corresponding to the plurality of electrode pads (3G, 3P, 3S).

Abstract: A thin-film capacitor structure (50) is joined to an electrode pad surface (2S) of an area array integrated circuit (2) having a plurality of electrode pads (3G, 3P, 3S) arranged in an area array on the electrode pad surface (2S). The thin-film capacitor structure (50) includes a thin-film capacitor (10) including a first sheet electrode (11), a second sheet electrode (13), and a thin-film dielectric layer (12) formed between the first sheet electrode (11) and the second sheet electrode (12), a first insulating film (21), a second insulating film (22), and a plurality of through holes (30P, 30G, 30S). The plurality of through holes (30P, 30G, 30S) are bored from the first insulating film (21) to the second insulating film (22) through the thin-film capacitor (10) and formed in positions corresponding to the plurality of electrode pads (3G, 3P, 3S).

Abstract: An intermediate connector includes a power source bus bar as an elongated thin plate to be connected to each power source pad of a semiconductor integrated circuit, a ground bus bar as an elongated thin plate to be connected to each ground pad of the semiconductor integrated circuit, a thin film insulator layer formed between the power source bus bar and the ground bus bar, and a conductive path portion as an elongated thin plate including a plurality of conductive paths to be connected to each signal pad of the semiconductor integrated circuit. The power source bus bar, the ground bus bar, and the conductive path portion are arranged in parallel correspondingly to a parallel arrangement of a power source pad row, a ground pad row, and a signal pad row of the semiconductor integrated circuit.

Abstract: An intermediate connector includes a power source bus bar as an elongated thin plate to be connected to each power source pad of a semiconductor integrated circuit, a ground bus bar as an elongated thin plate to be connected to each ground pad of the semiconductor integrated circuit, a thin film insulator layer formed between the power source bus bar and the ground bus bar, and a conductive path portion as an elongated thin plate including a plurality of conductive paths to be connected to each signal pad of the semiconductor integrated circuit. The power source bus bar, the ground bus bar, and the conductive path portion are arranged in parallel correspondingly to a parallel arrangement of a power source pad row, a ground pad row, and a signal pad row of the semiconductor integrated circuit.

Abstract: A multi-layered circuit board includes a first insulating layer, a second insulating layer, and a sheet capacitor that is located between the first insulating layer and the second insulating layer. The sheet capacitor includes a pair of electrodes that sandwich a dielectric. Lead wirings continue to the electrodes, respectively. The lead wirings are disposed on an opposite side of the first or the second insulating layer with respect to the sheet capacitor to overlap the electrodes when viewed from a stacking direction of the multi-layered circuit board. Because the lead wirings are arranged to overlap the electrodes in the stacking direction of the multi-layered circuit board, an ESL of the sheet capacitor is maintained low.

Abstract: A semiconductor device is provided with: a semiconductor integrated circuit having a bump mounting surface; and a thin-film capacitor portion connected to the bump mounting surface via a bump. The semiconductor integrated circuit includes a first power supply pad, and a second power supply pad. The thin-film capacitor portion includes a first electrode layer connected to the first power supply pad, a second electrode layer connected to the second power supply pad, and a dielectric layer formed between the first electrode layer and the second electrode layer. The semiconductor device is provided with an electric power supply path configured to supply electric power to the semiconductor integrated circuit, and a thin plate-shaped metal resistor portion provided in the electric power supply path and made from a metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer.

Abstract: A semiconductor device is provided with: a semiconductor integrated circuit having a bump mounting surface; and a thin-film capacitor portion connected to the bump mounting surface via a bump. The semiconductor integrated circuit includes a first power supply pad, and a second power supply pad. The thin-film capacitor portion includes a first electrode layer connected to the first power supply pad, a second electrode layer connected to the second power supply pad, and a dielectric layer formed between the first electrode layer and the second electrode layer. The semiconductor device is provided with an electric power supply path configured to supply electric power to the semiconductor integrated circuit, and a thin plate-shaped metal resistor portion provided in the electric power supply path and made from a metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer.

Abstract: A semiconductor memory device includes a thin-film capacitor disposed at a position facing a circuit surface of a memory chip except for a center pad region. The thin-film capacitor includes a first plane electrode, a thin-film dielectric layer, and a second plane electrode. The first plane electrode includes a first power supply input portion to which a power supply voltage of one polarity is provided, and a first power supply output portion disposed near the center pad region to output the power supply voltage of one polarity to a center pad. The second plane electrode is formed on the dielectric layer and includes a second power supply input portion to which the power supply voltage of the other polarity is provided, and a second power supply output portion disposed near the center pad region to apply the power supply voltage of the other polarity to the center pad.

Abstract: A semiconductor memory device includes a thin-film capacitor disposed at a position facing a circuit surface of a memory chip except for a center pad region. The thin-film capacitor includes a first plane electrode, a thin-film dielectric layer, and a second plane electrode. The first plane electrode includes a first power supply input portion to which a power supply voltage of one polarity is provided, and a first power supply output portion disposed near the center pad region to output the power supply voltage of one polarity to a center pad. The second plane electrode is formed on the dielectric layer and includes a second power supply input portion to which the power supply voltage of the other polarity is provided, and a second power supply output portion disposed near the center pad region to apply the power supply voltage of the other polarity to the center pad.

Abstract: A multi-layered circuit board includes a first insulating layer, a second insulating layer, and a sheet capacitor that is located between the first insulating layer and the second insulating layer. The sheet capacitor includes a pair of electrodes that sandwich a dielectric. Lead wirings continue to the electrodes, respectively. The lead wirings are disposed on an opposite side of the first or the second insulating layer with respect to the sheet capacitor to overlap the electrodes when viewed from a stacking direction of the multi-layered circuit board. Because the lead wirings are arranged to overlap the electrodes in the stacking direction of the multi-layered circuit board, an ESL of the sheet capacitor is maintained low.

Abstract: A power supply wiring structure of a semiconductor device including a semiconductor chip flip-chip mounted on a substrate decreases the characteristic impedance of internal wiring and thereby increases the noise reduction effect, while achieving low impedance during high frequency power supply operation. A semiconductor device has an inner power supply plate structure on a first insulating film on a protection film of a semiconductor chip, in an inner region of a plurality of peripheral electrode pads on a mounting surface of the semiconductor chip as viewed in plan, for supplying power to the semiconductor chip. The inner power supply plate structure includes a first power supply plate on the first insulating film, a second insulating film on the first power supply plate, and a second power supply plate on the second insulating film.

Abstract: A power supply wiring structure of a semiconductor device including a semiconductor chip flip-chip mounted on a substrate decreases the characteristic impedance of internal wiring and thereby increases the noise reduction effect, while achieving low impedance during high frequency power supply operation. A semiconductor device has an inner power supply plate structure on a first insulating film on a protection film of a semiconductor chip, in an inner region of a plurality of peripheral electrode pads on a mounting surface of the semiconductor chip as viewed in plan, for supplying power to the semiconductor chip. The inner power supply plate structure includes a first power supply plate on the first insulating film, a second insulating film on the first power supply plate, and a second power supply plate on the second insulating film.

Abstract: A semiconductor device includes a semiconductor chip, an interposer, a surface circuit pattern, and a post array. The surface circuit pattern is formed on one surface of the interposer and includes chip side pads connected to an external connection pad of the semiconductor chip, junction pads, and interconnecting lines having an end connected to the chip side pads and another end connected to the junction pads. The interconnecting lines extend from the chip side pads toward an outer edge of the interposer. The post array includes conducting paths and insulating resin insulating the conductive paths from each other. The post array is arranged such that the conductive paths extend in a direction intersecting with the surface of the interposer. The conducting paths each have an end connected to the junction pad and another end to be connected to the printed wiring board.

Abstract: A semiconductor device includes a semiconductor chip, an interposer, a surface circuit pattern, and a post array. The surface circuit pattern is formed on one surface of the interposer and includes chip side pads connected to an external connection pad of the semiconductor chip, junction pads, and interconnecting lines having an end connected to the chip side pads and another end connected to the junction pads. The interconnecting lines extend from the chip side pads toward an outer edge of the interposer. The post array includes conducting paths and insulating resin insulating the conductive paths from each other. The post array is arranged such that the conductive paths extend in a direction intersecting with the surface of the interposer. The conducting paths each have an end connected to the junction pad and another end to be connected to the printed wiring board.

Abstract: A semiconductor device includes an Si substrate having a first surface provided with semiconductor elements, such as a CMOS transistor and a diode, and a second surface opposite to the first surface. On one of the first and the second surfaces, a bypass capacitor is formed. The bypass capacitor includes a Vcc power supply layer and a GND layer which serve to supply a power supply voltage to the semiconductor element, and a high dielectric constant layer sandwiched between the Vcc power supply layer and the GND layer.

Abstract: A BSC macrostructure for three-dimensional wiring includes a BSC (boundary scan cell) and an aperture electrode for electrode connection which is connected to the BSC.

Abstract: A wiring structure of a substrate adapted to mount a plurality of integrated circuits has a signal wire for connecting the integrated circuits to each other, first and second power supply layers faced to each other, and return path wires arranged generally in parallel to the signal wire. One of the return path wires has opposite terminal ends connected to the first power supply layer (Vcc layer). The other return path wire has opposite terminal ends connected to the second power supply layer (GND layer).

Abstract: A semiconductor device includes an Si substrate having a first surface provided with semiconductor elements, such as a CMOS transistor and a diode, and a second surface opposite to the first surface. On one of the first and the second surfaces, a bypass capacitor is formed. The bypass capacitor includes a Vcc power supply layer and a GND layer which serve to supply a power supply voltage to the semiconductor element, and a high dielectric constant layer sandwiched between the Vcc power supply layer and the GND layer.

Abstract: In a method of manufacturing a semiconductor device which has rear electrodes extended from a front surface to a rear surface of a substrate, the rear electrodes are formed from a side of the front surface by forming a groove on the front surface, by forming a metal film on the groove, and by removing the substrate from a rear surface until the metal film is exposed on a bottom of the groove.

Abstract: A semiconductor device includes an Si substrate having a first surface provided with semiconductor elements, such as a CMOS transistor and a diode, and a second surface opposite to the first surface. On one of the first and the second surfaces, a bypass capacitor is formed. The bypass capacitor includes a Vcc power supply layer and a GND layer which serve to supply a power supply voltage to the semiconductor element, and a high dielectric constant layer sandwiched between the Vcc power supply layer and the GND layer.