Patents by Inventor Seisei Oyamada

Seisei Oyamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090230780
    Abstract: In a power controller for a mounting substrate adapted to mount an integrated circuit includes I/O pads mounted on a semiconductor substrate as the mounting substrate, and a Vcc1 electric circuit system mounted on the semiconductor substrate, an isolator portion is included in the power controller and is connected between one of the I/O pads and the Vcc1 electric circuit system. Another isolator portion may be connected between the other I/O pad and another Vcc3 electric circuit system.
    Type: Application
    Filed: March 17, 2008
    Publication date: September 17, 2009
    Inventor: Seisei Oyamada
  • Publication number: 20090229866
    Abstract: A wiring structure of a substrate adapted to mount a plurality of integrated circuits has a signal wire for connecting the integrated circuits to each other, first and second power supply layers faced to each other, and return path wires arranged generally in parallel to the signal wire. One of the return path wires has opposite terminal ends connected to the first power supply layer (Vcc layer). The other return path wire has opposite terminal ends connected to the second power supply layer (GND layer).
    Type: Application
    Filed: March 17, 2008
    Publication date: September 17, 2009
    Inventor: Seisei Oyamada
  • Publication number: 20090235135
    Abstract: A BSC macrostructure for three-dimensional wiring includes a BSC (boundary scan cell) and an aperture electrode for electrode connection which is connected to the BSC.
    Type: Application
    Filed: March 17, 2008
    Publication date: September 17, 2009
    Inventor: Seisei Oyamada
  • Patent number: 6359490
    Abstract: The purpose of the present invention is to provide a clamping circuit which has a simple circuit design, with which the clamping voltage range can be easily adjusted, and which can operate at reduced power consumption, as well as interface circuit that makes use of the clamping circuit. NMOS transistor NT1 and diode D1 are connected in series between the feed line of power source voltage Vcc and input terminal Tin, and diode D2 and PMOS transistor PT1 are connected in series between input terminal Tin and ground voltage GND. The divider voltages VND1, and VND2 obtained from resistive elements R1, R2 and R3 connected in series are applied to the control terminals of transistors NT1 and PT1, respectively. Also, transistor NT2 is connected in parallel to resistive element R2. By means of control voltage VB input to the control terminal of NT2, the divider voltages are controlled, and the range of the clamping voltage can be controlled.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: March 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Seisei Oyamada
  • Patent number: 6316984
    Abstract: An interface circuit which can transmit signals at high speed in a back plane application, which, in turn, can transmit signals among multiple circuit substrates via the transmission lines on a back board. Card 52 of the present invention has input circuit 92, wiring 212, and clamping circuit 402. Wiring 212 is connected to the input of input circuit 92, and clamping circuit 402 is connected to wiring 212. A signal is transmitted from transmission line 3 on back board 2 to wiring 212 via socket 42. However, when the transmitted signal rises or drops significantly, the signal is clamped by clamping circuit 402 so that it will not go outside a certain voltage range. The vibration amplitude of the signal becomes small. Consequently, the time needed for the input potential of input circuit 92 to be stabilized can be reduced and signals can be transmitted at high speed.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: November 13, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Seisei Oyamada