Patents by Inventor Seisho Yasukawa

Seisho Yasukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210168051
    Abstract: Included are a communication quality requirement derivation unit that derives, for a specific service session between a server and a terminal, a communication quality requirement to be satisfied between the server and the terminal based on a requested quality of experience of the specific service session; a monitoring unit that monitors a communication quality of the specific service session between the server and the terminal; a determination unit that determines whether the communication quality of the specific service session satisfies the communication quality requirement derived for the specific service session; and a control unit that controls, when the communication quality of the specific service session does not satisfy the communication quality requirement derived for the specific service session, a communication route used for the specific service session between the server and the terminal so as to satisfy the communication quality requirement.
    Type: Application
    Filed: August 2, 2019
    Publication date: June 3, 2021
    Inventors: Takafumi OKUYAMA, Hiroshi INOUE, Kenichi ENDO, Toshiaki Tsuchiya, Seisho YASUKAWA
  • Publication number: 20210006486
    Abstract: A computer executes a first determination procedure determining a first link which at least partially overlaps a disaster area representing a range reached by an influence of a predetermined disaster, among links constituting a network, a second determination procedure determining a second link which at least partially overlaps a road area representing a range of a road width of a predetermined road used to recover from the disaster, among the links constituting the network, a route search procedure searching for a plurality of routes from a start point node to an end point node constituting the network, a grouping procedure grouping the plurality of routes searched for by the route search procedure into groups depending on a first parameter value that is based on the first link included in the routes, a computing procedure computing, for each of the plurality of routes searched for by the route search procedure, a second parameter value that is based on the first link and the second link included in the rout
    Type: Application
    Filed: February 13, 2019
    Publication date: January 7, 2021
    Inventors: Takuma TSUBAKI, Mika ISHIZUKA, Hiroshi INOUE, Seisho YASUKAWA
  • Patent number: 7792099
    Abstract: A method of establishing a multicast transfer route is disclosed that can reduce the cost of entire route under a constraint on delay incurred between starting point and ending points. The method includes the steps of: computing the shortest route with respect to delay connecting the starting point and the plural ending points based on measurement result; computing delay from a node on the shortest route to each ending point and the greatest delay; removing, if the greatest delay satisfies a delay condition, the greatest-cost route from the shortest route in accordance with selection criteria effective for cost reduction; dividing the multicast transfer route into two route trees; and establishing separately computed route as a complementary route that complement the removed route for connecting the two route trees. A method of multicast label switching for realizing the above method is also disclosed.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: September 7, 2010
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Koji Sugisono, Masanori Uga
  • Patent number: 7693074
    Abstract: A multicast communication path calculation method is disclosed which includes the steps of: obtaining minimum delay paths from a source node to each destination node; selecting, as candidate nodes of a rendezvous point node, nodes on one of the obtained minimum delay paths; for each candidate node, calculating minimum delay paths from the candidate node to each destination node, and obtaining a difference between the maximum value and the minimum value among delays of the calculated minimum delay paths; selecting, as the rendezvous point node, a candidate node by which the difference is smallest; and outputting a minimum delay path from the source node to the rendezvous point node and minimum delay paths from the rendezvous point node to each destination node.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: April 6, 2010
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Koji Sugisono, Masanori Uga
  • Patent number: 7652998
    Abstract: A multicast communication path calculation method is disclosed which includes the steps of: obtaining minimum delay paths from a source node to each destination node; selecting, as candidate nodes of a rendezvous point node, nodes on one of the obtained minimum delay paths; for each candidate node, calculating minimum delay paths from the candidate node to each destination node, and obtaining a difference between the maximum value and the minimum value among delays of the calculated minimum delay paths; selecting, as the rendezvous point node, a candidate node by which the difference is smallest; and outputting a minimum delay path from the source node to the rendezvous point node and minimum delay paths from the rendezvous point node to each destination node.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: January 26, 2010
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Koji Sugisono, Masanori Uga
  • Patent number: 7583601
    Abstract: A method of establishing a multicast transfer route is disclosed that can reduce the cost of entire route under a constraint on delay incurred between starting point and ending points. The method includes the steps of: computing the shortest route with respect to delay connecting the starting point and the plural ending points based on measurement result; computing delay from a node on the shortest route to each ending point and the greatest delay; removing, if the greatest delay satisfies a delay condition, the greatest-cost route from the shortest route in accordance with selection criteria effective for cost reduction; dividing the multicast transfer route into two route trees; and establishing separately computed route as a complementary route that complement the removed route for connecting the two route trees. A method of multicast label switching for realizing the above method is also disclosed.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: September 1, 2009
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Koji Sugisono, Masanori Uga
  • Publication number: 20090028149
    Abstract: A method of establishing a multicast transfer route is disclosed that can reduce the cost of entire route under a constraint on delay incurred between starting point and ending points. The method includes the steps of: computing the shortest route with respect to delay connecting the starting point and the plural ending points based on measurement result; computing delay from a node on the shortest route to each ending point and the greatest delay; removing, if the greatest delay satisfies a delay condition, the greatest-cost route from the shortest route in accordance with selection criteria effective for cost reduction; dividing the multicast transfer route into two route trees; and establishing separately computed route as a complementary route that complement the removed route for connecting the two route trees. A method of multicast label switching for realizing the above method is also disclosed.
    Type: Application
    Filed: September 25, 2008
    Publication date: January 29, 2009
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Seisho YASUKAWA, Koji Sugisono, Masanori Uga
  • Patent number: 7474664
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: January 6, 2009
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka
  • Patent number: 7339935
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: March 4, 2008
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka
  • Publication number: 20080013465
    Abstract: A multicast communication path calculation method is disclosed which includes the steps of: obtaining minimum delay paths from a source node to each destination node; selecting, as candidate nodes of a rendezvous point node, nodes on one of the obtained minimum delay paths; for each candidate node, calculating minimum delay paths from the candidate node to each destination node, and obtaining a difference between the maximum value and the minimum value among delays of the calculated minimum delay paths; selecting, as the rendezvous point node, a candidate node by which the difference is smallest; and outputting a minimum delay path from the source node to the rendezvous point node and minimum delay paths from the rendezvous point node to each destination node.
    Type: Application
    Filed: July 12, 2007
    Publication date: January 17, 2008
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORP.
    Inventors: Seisho YASUKAWA, Koji SUGISONO, Masanori UGA
  • Patent number: 7292576
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: November 6, 2007
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka
  • Patent number: 7136391
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: November 14, 2006
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka
  • Publication number: 20060147204
    Abstract: A method of establishing a multicast transfer route is disclosed that can reduce the cost of entire route under a constraint on delay incurred between starting point and ending points. The method includes the steps of: computing the shortest route with respect to delay connecting the starting point and the plural ending points based on measurement result; computing delay from a node on the shortest route to each ending point and the greatest delay; removing, if the greatest delay satisfies a delay condition, the greatest-cost route from the shortest route in accordance with selection criteria effective for cost reduction; dividing the multicast transfer route into two route trees; and establishing separately computed route as a complementary route that complement the removed route for connecting the two route trees. A method of multicast label switching for realizing the above method is also disclosed.
    Type: Application
    Filed: February 6, 2004
    Publication date: July 6, 2006
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Seisho Yasukawa, Koji Sugisono, Masanori Uga
  • Publication number: 20050083939
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Application
    Filed: October 22, 2004
    Publication date: April 21, 2005
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nebeshima, Eiji Oki, Naoaki Yamanaka
  • Publication number: 20050053096
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Application
    Filed: October 22, 2004
    Publication date: March 10, 2005
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka
  • Publication number: 20050053067
    Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.
    Type: Application
    Filed: October 22, 2004
    Publication date: March 10, 2005
    Inventors: Seisho Yasukawa, Naoki Takaya, Masayoshi Nabeshima, Eiji Oki, Naoaki Yamanaka
  • Publication number: 20040218536
    Abstract: A multicast communication path calculation method is disclosed which includes the steps of: obtaining minimum delay paths from a source node to each destination node; selecting, as candidate nodes of a rendezvous point node, nodes on one of the obtained minimum delay paths; for each candidate node, calculating minimum delay paths from the candidate node to each destination node, and obtaining a difference between the maximum value and the minimum value among delays of the calculated minimum delay paths; selecting, as the rendezvous point node, a candidate node by which the difference is smallest; and outputting a minimum delay path from the source node to the rendezvous point node and minimum delay paths from the rendezvous point node to each destination node.
    Type: Application
    Filed: December 10, 2003
    Publication date: November 4, 2004
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORP.
    Inventors: Seisho Yasukawa, Koji Sugisono, Masanori Uga
  • Patent number: 5892604
    Abstract: An ATM switch includes a plurality of input line corresponding units, a plurality of output line corresponding units, and a wavelength shifting unit. The wavelength shifting unit is arranged between the input line corresponding units and the output line corresponding units to shift optical signals having different wavelengths in a plurality of wavelength-multiplexed optical signals arriving from the input line corresponding units and output the wavelength-multiplexed optical signals. Each input line corresponding unit includes an input-side basic switch for distributing N (N is a positive integer) cells respectively input to input ports to N lines, an electro-optic converter for converting the cells into optical signals having different wavelengths in units of N lines, and a multiplexer for multiplexing the optical signals into one wavelength-multiplexed optical signal.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: April 6, 1999
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Naoaki Yamanaka, Kohei Shiomoto, Eiji Oki, Seisho Yasukawa