Patents by Inventor Seiyon Kim

Seiyon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11139400
    Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 5, 2021
    Assignee: Google LLC
    Inventors: Seiyon Kim, Rafael Rios, Fahmida Ferdousi, Kelin J. Kuhn
  • Publication number: 20210257457
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.
    Type: Application
    Filed: April 12, 2021
    Publication date: August 19, 2021
    Inventors: Seung Hoon Sung, Seiyon Kim, Kelin J. Kuhn, Willy Rachmady, Jack T. Kavalieros
  • Publication number: 20210226006
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Application
    Filed: April 8, 2021
    Publication date: July 22, 2021
    Inventors: Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani, Titash Rakshit, Peter Chang, Willy Rachmady
  • Patent number: 11024714
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 1, 2021
    Assignee: Sony Corporation
    Inventors: Seung Hoon Sung, Seiyon Kim, Kelin J. Kuhn, Willy Rachmady, Jack T. Kavalieros
  • Patent number: 11004978
    Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Glenn Glass, Karthik Jambunathan, Anand Murthy, Chandra Mohapatra, Seiyon Kim
  • Patent number: 11004868
    Abstract: Memory field-effect transistors and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor substrate and a ferroelectric gate insulator of a memory field-effect transistor formed within a trench having walls defined by spacers and a base defined by the semiconductor substrate. The apparatus further includes a gate conductor formed on the ferroelectric gate insulator. The ferroelectric gate insulator is to separate a bottom surface of the gate conductor and the substrate.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Uygar E. Avci, Joshua M. Howard, Ian A. Young, Daniel H. Morris
  • Patent number: 10991799
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 27, 2021
    Assignee: Sony Corporation
    Inventors: Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani, Titash Rakshit, Peter Chang, Willy Rachmady
  • Publication number: 20210050418
    Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
    Type: Application
    Filed: September 4, 2020
    Publication date: February 18, 2021
    Inventors: Seiyon KIM, Kelin J. KUHN, Tahir GHANI, Anand S. MURTHY, Mark ARMSTRONG, Rafael RIOS, Abhijit Jayant PETHE, Willy RACHMADY
  • Publication number: 20210043755
    Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Inventors: Rishabh MEHANDRU, Patrick MORROW, Ranjith KUMAR, Cory E. WEBER, Seiyon KIM, Stephen M. CEA, Tahir GHANI
  • Publication number: 20210036137
    Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Inventors: Stephen M. CEA, Cory E. WEBER, Patrick H. KEYS, Seiyon KIM, Michael G. HAVERTY, Sadasivan SHANKAR
  • Patent number: 10847635
    Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea, Tahir Ghani
  • Patent number: 10840366
    Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
  • Patent number: 10825752
    Abstract: Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Lei Jiang, Edwin B. Ramayya, Daniel Pantuso, Rafael Rios, Kelin J. Kuhn, Seiyon Kim
  • Patent number: 10804357
    Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: October 13, 2020
    Assignee: Sony Corporation
    Inventors: Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios, Abhijit Jayant Pethe, Willy Rachmady
  • Publication number: 20200321446
    Abstract: Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode.
    Type: Application
    Filed: September 28, 2017
    Publication date: October 8, 2020
    Inventors: Seiyon KIM, Uygar E. AVCI, Joshua M. HOWARD, Ian A. YOUNG, Daniel H. MORRIS
  • Patent number: 10784352
    Abstract: Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Sanaz K. Gardner, Willy Rachmady, Van H. Le, Matthew V. Metz, Seiyon Kim, Ashish Agrawal, Jack T. Kavalieros
  • Patent number: 10770458
    Abstract: Techniques are disclosed for forming nanowire transistor architectures in which the presence of gate material between neighboring nanowires is eliminated or otherwise reduced. In some examples, neighboring nanowires can be formed sufficiently proximate one another such that their respective gate dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous dielectric layer shared by the neighboring nanowires. In some cases, a given gate dielectric layer may be of a multi-layer configuration, having two or more constituent dielectric layers. Thus, in some examples, the gate dielectric layers of neighboring nanowires may be formed such that one or more constituent dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous constituent dielectric layer shared by the neighboring nanowires.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Tahir Ghani, Szuya S. Liao, Seiyon Kim
  • Publication number: 20200235243
    Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.
    Type: Application
    Filed: September 29, 2017
    Publication date: July 23, 2020
    Applicant: INTEL CORPORATION
    Inventors: Uygar E. Avci, Joshua M. Howard, Seiyon Kim, Ian A. Young
  • Publication number: 20200227520
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Inventors: Kelin J. KUHN, Seiyon KIM, Rafael RIOS, Stephen M. CEA, Martin D. GILES, Annalisa CAPPELLANI, Titash RAKSHIT, Peter CHANG, Willy RACHMADY
  • Publication number: 20200203358
    Abstract: Described is an apparatus which comprises: a first layer comprising a metal; a second layer comprising a first para-electric material, the second layer adjacent to the first layer; and a third layer comprising a second para-electric material, the third layer adjacent to the second layer, wherein the first para-electric material is different from the second para-electric material.
    Type: Application
    Filed: September 27, 2017
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: Uygar E. Avci, Joshua M. Howard, Seiyon Kim, Ian A. Young