Patents by Inventor Selcuk Kose

Selcuk Kose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190199384
    Abstract: A system and method for adaptively utilizing transmitter windowing, receiver windowing and alignment signals for minimizing interference and maximizing capacity and energy efficiency based upon the received power ratios of links in adjacent bands of a cellular communication network.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 27, 2019
    Applicant: University of South Florida
    Inventors: Berker Pekoz, Selcuk Kose, Huseyin Arslan
  • Publication number: 20190199383
    Abstract: A system and method for adaptively utilizing transmitter windowing, receiver windowing and alignment signals for minimizing interference and maximizing capacity and energy efficiency based upon the received power ratios of links in adjacent bands of a cellular communication network.
    Type: Application
    Filed: October 22, 2018
    Publication date: June 27, 2019
    Applicant: University of South Florida
    Inventors: Berker Pekoz, Selcuk Kose, Huseyin Arslan
  • Publication number: 20180316489
    Abstract: Methods and systems are provided for a security adaptive (SA) voltage converter that receives input power from a power source and provides power to a cryptographic system. The SA voltage converter triggers countermeasures against leakage power analysis (LPA) attacks that slow down an operating frequency of the cryptographic circuit. When an LPA attack is detected, a discharging resistor sinks redundant current to alter the signature of load power dissipation of at the input to the SA voltage converter system. The SA voltage converter includes a converter reshuffling converter. The power dissipation induced by the discharging resistor, as measured at the input received from the power source, is scrambled by the SA voltage converter to increase noise inserted into the input power and to alter the power profile that is measured for the cryptographic circuit.
    Type: Application
    Filed: April 30, 2018
    Publication date: November 1, 2018
    Applicant: University of South Florida
    Inventors: Selcuk Kose, Weize Yu
  • Publication number: 20180314860
    Abstract: Methods and systems are provided for a charge withholding converter reshuffling technique that decorrelates input power of a multi-phase switched capacitor (SC) voltage converter relative to the output power provided to a load. The load may be a cryptographic device. The technique provides a countermeasure against power analysis attacks. A controller including a first random number generator coupled to the stages of the SC voltage converter controls gating for charging a first subset of the stages. A controller including a second random number generator coupled the stages of the SC voltage converter controls gating for discharging a second subset the stages. A number of the switched capacitor stages maintain their charge beyond the switch period in which they are charged. The SC voltage converter withholds a random portion of input charge and delivers this charge to the load after a random time period.
    Type: Application
    Filed: April 30, 2018
    Publication date: November 1, 2018
    Applicant: University of South Florida
    Inventors: Selcuk Kose, Weize Yu
  • Publication number: 20180316488
    Abstract: Methods and systems are provided for single false key-controlled (SFKC) aggressive voltage scaling (AVS) and multiple parallel false key controlled (MPFKC) AVS countermeasure systems. When a plaintext value is input into a cryptographic circuit for modification by a correct key, power supplied to the cryptographic circuit is scaled based on a result of the plaintext value modified by a false key or by a random number of parallel false keys, which occurs during every clock cycle. The scaling may be triggered when the operating frequency of the cryptographic circuit falls below a threshold, which indicates occurrence of a leakage power attack. A key that is detectable within a power trace of the scaled power provided to the cryptographic circuit, with a highest correlation coefficient relative to a known key, is a key other than the correct key. The MPFKC AVS technique also inhibits unriddling of the input power scaling scheme.
    Type: Application
    Filed: April 30, 2018
    Publication date: November 1, 2018
    Applicant: University of South Florida
    Inventors: Selcuk Kose, Weize Yu
  • Patent number: 9812954
    Abstract: Dynamic power management techniques and voltage converter architectures are described to provide a secure and efficient on-chip power delivery system. In aspects of the embodiments, converter-gating adaptively turns on and off individual stages of an interleaved switched-capacitor voltage converter based on workload information to improve voltage conversion efficiency. Converter-gating is further utilized as a countermeasure against side channel power analysis attacks by pseudo-randomly controlling converter activity. The embodiments also improve the response time of converters during transient load changes by adaptively configuring the conversion ratio of a switched capacitor (SC) voltage converter.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 7, 2017
    Assignee: UNIVERSITY OF SOUTH FLORIDA
    Inventors: Selcuk Kose, Orhun Aras Uzun
  • Patent number: 9748837
    Abstract: Dynamic power management techniques and voltage converter architectures are described to provide a secure and efficient on-chip power delivery system. In aspects of the embodiments, converter-gating is used to adaptively turn individual interleaved switched-capacitor stages of a voltage converter on and off based on workload information to improve voltage conversion efficiency. Further, as a countermeasure against machine learning based differential power analysis attacks, for example, control signals provided to a number of the interleaved switched-capacitor stages are delayed to reduce the risk of low power trace entropy (PTE). A higher PTE value is maintained regardless of the phase difference between an attacker's sampling rate and the operating frequency, providing an additional layer of security.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: August 29, 2017
    Assignee: UNIVERSITY OF SOUTH FLORIDA
    Inventors: Selcuk Kose, Orhun Aras Uzun, Weize Yu
  • Patent number: 9372490
    Abstract: A system and method for adaptive activity management of on-chip voltage regulators based upon the workload information is provided to force each on-chip regulator to operate in its most power-efficient load current. In the proposed regulator-gating technique, regulators are adaptively turned ON when the current demand is high and turned OFF when the current demand is low to improve the voltage conversion efficiency. With the proposed regulator-gating system and method, the overall voltage conversion efficiency from the battery or off-chip power supply to the output of the on-chip voltage regulators experiences an approximately 3 times improvement over the prior art techniques.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: June 21, 2016
    Assignee: University of South Florida
    Inventors: Selcuk Kose, Orhun Aras Uzun
  • Patent number: 9007140
    Abstract: The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: April 14, 2015
    Assignees: University of South Florida, University of Rochester
    Inventors: Selcuk Kose, Eby G. Friedman
  • Patent number: 8922272
    Abstract: A system and method for adaptive activity management of on-chip voltage regulators based upon the workload information is provided to force each on-chip regulator to operate in its most power-efficient load current. In the proposed regulator-gating technique, regulators are adaptively turned ON when the current demand is high and turned OFF when the current demand is low to improve the voltage conversion efficiency. With the proposed regulator-gating system and method, the overall voltage conversion efficiency from the battery or off-chip power supply to the output of the on-chip voltage regulators experiences an approximately 3 times improvement over the prior art techniques.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: December 30, 2014
    Assignee: University of South Florida
    Inventors: Selcuk Kose, Orhun Aras Uzun