Patents by Inventor Se-myeong Jang
Se-myeong Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11676816Abstract: A method of forming a semiconductor device includes forming first sacrificial patterns on a lower structure, forming first remaining mask layers having a āUā shape between the first sacrificial patterns to be in contact with the first sacrificial patterns, forming first remaining mask patterns by pattering the first remaining mask layers, each of the first remaining mask patterns including a horizontal portion, parallel to an upper surface of the lower structure, and a vertical portion, perpendicular to the upper surface of the lower structure, forming second mask patterns spaced apart from the vertical portions of the first remaining mask patterns, removing the first sacrificial patterns remaining after forming the second mask patterns, and forming first mask patterns by etching the horizontal portions of the first remaining mask patterns.Type: GrantFiled: August 2, 2019Date of Patent: June 13, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sung Min Park, Se Myeong Jang, Bong Soo Kim, Je Min Park
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Patent number: 11355349Abstract: A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.Type: GrantFiled: September 25, 2020Date of Patent: June 7, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Park, Se Myeong Jang, Bong Soo Kim, Je Min Park
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Publication number: 20210013046Abstract: A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.Type: ApplicationFiled: September 25, 2020Publication date: January 14, 2021Inventors: Sung-Min PARK, Se Myeong JANG, Bong Soo KIM, Je Min PARK
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Patent number: 10867802Abstract: A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.Type: GrantFiled: January 17, 2019Date of Patent: December 15, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Park, Se Myeong Jang, Bong Soo Kim, Je Min Park
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Publication number: 20200152462Abstract: A method of forming a semiconductor device includes forming first sacrificial patterns on a lower structure, forming first remaining mask layers having a āUā shape between the first sacrificial patterns to be in contact with the first sacrificial patterns, forming first remaining mask patterns by pattering the first remaining mask layers, each of the first remaining mask patterns including a horizontal portion, parallel to an upper surface of the lower structure, and a vertical portion, perpendicular to the upper surface of the lower structure, forming second mask patterns spaced apart from the vertical portions of the first remaining mask patterns, removing the first sacrificial patterns remaining after forming the second mask patterns, and forming first mask patterns by etching the horizontal portions of the first remaining mask patterns.Type: ApplicationFiled: August 2, 2019Publication date: May 14, 2020Inventors: Sung Min Park, Se Myeong Jang, Bong Soo Kim, Je Min Park
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Publication number: 20200035499Abstract: A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.Type: ApplicationFiled: January 17, 2019Publication date: January 30, 2020Inventors: Sung-Min PARK, Se Myeong JANG, Bong Soo KIM, Je Min PARK
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Publication number: 20190355813Abstract: Provided are semiconductor devices including device isolation layers. The semiconductor device includes a substrate having a cell region and a core/peripheral region, a first active region in the cell region of the substrate, a first device isolation layer that defines the first active region, a second active region in the core/peripheral region of the substrate; and a second device isolation layer that defines the second active region. A height from a lower surface of the substrate to an upper end of the first device isolation layer in a first direction that is perpendicular to the lower surface of the substrate is less than or equal to a height from the lower surface of the substrate to an upper end of the first active region in the first direction.Type: ApplicationFiled: December 12, 2018Publication date: November 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Se-myeong JANG, Jun-hyeok AHN, Bong-soo KIM, Hyo-bin PARK, Myoung-seob SHIM
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Patent number: 9972527Abstract: A semiconductor device includes a substrate including a plurality of active areas. A conductive pattern is in contact with an active area. First and second conductive line structures face first and second side walls of the conductive pattern. An air spacer is disposed between the first and second side walls. The first and second conductive line structures include a conductive line and a conductive line mask layer. The conductive line mask layer includes a lower portion having a first width and an upper portion having a second width narrower than the first width. The air spacer includes a first air spacer disposed on a side wall of the lower portion of the conductive line mask layer and a second air spacer disposed on a side wall of the upper portion of the conductive line mask layer. The second air spacer is connected with the first air spacer.Type: GrantFiled: September 13, 2016Date of Patent: May 15, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-Eun Kim, Yong-Kwan Kim, Se-Myeong Jang, Yoo-Sang Hwang, Bong-Soo Kim
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Publication number: 20170154805Abstract: A semiconductor device includes a substrate including a plurality of active areas. A conductive pattern is in contact with an active area. First and second conductive line structures face first and second side walls of the conductive pattern. An air spacer is disposed between the first and second side walls. The first and second conductive line structures include a conductive line and a conductive line mask layer. The conductive line mask layer includes a lower portion having a first width and an upper portion having a second width narrower than the first width. The air spacer includes a first air spacer disposed on a side wall of the lower portion of the conductive line mask layer and a second air spacer disposed on a side wall of the upper portion of the conductive line mask layer. The second air spacer is connected with the first air spacer.Type: ApplicationFiled: September 13, 2016Publication date: June 1, 2017Inventors: KYUNG-EUN KIM, Yong-Kwan Kim, Se-Myeong Jang, Yoo-Sang Hwang, Bong-Soo Kim
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Patent number: 9634012Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.Type: GrantFiled: February 4, 2016Date of Patent: April 25, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Jin Park, Chan-sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung, Dae-Ik Kim, Bong-Soo Kim, Yong-Kwan Kim, Eun-Jung Kim, Se-Myeong Jang, Min-su Choi, Sung-Hee Han, Yoo-Sang Hwang
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Patent number: 9570510Abstract: An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other.Type: GrantFiled: May 28, 2015Date of Patent: February 14, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Jung Kim, Se-Myeong Jang, Dae-Ik Kim, Je-Min Park, Yoo-Sang Hwang
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Publication number: 20170025420Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.Type: ApplicationFiled: February 4, 2016Publication date: January 26, 2017Inventors: Tae-Jin Park, Chan-sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung, Dae-Ik Kim, Bong-Soo Kim, Yong-Kwan Kim, Eun-Jung Kim, Se-Myeong Jang, Min-su Choi, Sung-Hee Han, Yoo-Sang Hwang
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Patent number: 9536884Abstract: A semiconductor device can include a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second direction, the plurality of active regions being repeatedly and separately positioned along the first and second directions, an isolation film defining the plurality of active regions, a plurality of word lines extending across the plurality of active regions and the isolation film, and a positive fixed charge containing layer covering at least a portion of the plurality of word lines, respectively.Type: GrantFiled: August 4, 2014Date of Patent: January 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Soo Kim, Dong-Soo Woo, Se-myeong Jang
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Patent number: 9281362Abstract: According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region in the peripheral circuit region, and at least one deep trench isolation region. The first active regions may be aligned to extend longitudinally in a first direction in the cell array region. The at least one deep trench isolation region is recessed in the substrate to a level lower than those of other points of a bottom surface of the second trench isolation region in the peripheral circuit region. The at least one deep trench isolation region includes at least one point that is spaced apart in the first direction from a corresponding one of the first active regions.Type: GrantFiled: May 23, 2014Date of Patent: March 8, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Ja-Young Lee, Se-myeong Jang
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Publication number: 20160020251Abstract: An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other.Type: ApplicationFiled: May 28, 2015Publication date: January 21, 2016Inventors: Eun-Jung KIM, Se-Myeong JANG, Dae-Ik KIM, Je-Min PARK, Yoo-Sang HWANG
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Publication number: 20150194438Abstract: A semiconductor device can include a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second direction, the plurality of active regions being repeatedly and separately positioned along the first and second directions, an isolation film defining the plurality of active regions, a plurality of word lines extending across the plurality of active regions and the isolation film, and a positive fixed charge containing layer covering at least a portion of the plurality of word lines, respectively.Type: ApplicationFiled: August 4, 2014Publication date: July 9, 2015Inventors: Jun-Soo Kim, Dong-Soo Woo, Se-myeong Jang
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Publication number: 20150091127Abstract: According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region in the peripheral circuit region, and at least one deep trench isolation region. The first active regions may be aligned to extend longitudinally in a first direction in the cell array region. The at least one deep trench isolation region is recessed in the substrate to a level lower than those of other points of a bottom surface of the second trench isolation region in the peripheral circuit region. The at least one deep trench isolation region includes at least one point that is spaced apart in the first direction from a corresponding one of the first active regions.Type: ApplicationFiled: May 23, 2014Publication date: April 2, 2015Inventors: Ja-Young LEE, Se-myeong JANG
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Patent number: 8987907Abstract: A semiconductor device may include a semiconductor layer including at least one unit device, a first interconnection on the semiconductor layer and electrically connected to the at least one unit device, a diffusion barrier layer on the first interconnection, an intermetallic dielectric layer on the diffusion barrier layer, a plug in a first region of the intermetallic dielectric layer and passing through the diffusion barrier layer so that a bottom surface thereof contacts the first interconnection, and a first dummy plug in a second region of the intermetallic dielectric layer, passing through the diffusion barrier layer, and disposed apart from the first interconnection so that a bottom surface of the first dummy plug does not contact the first interconnection.Type: GrantFiled: February 26, 2013Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Min-sung Kang, Se-myeong Jang
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Patent number: 8928073Abstract: A semiconductor device includes a substrate partitioned into a cell region, a peripheral circuit region, and an interface region between the cell region and the peripheral circuit region. A guard ring is provided in the interface region of the substrate and surrounds the cell region. A first gate structure is in the cell region, and a second gate structure is in the peripheral circuit region.Type: GrantFiled: March 6, 2013Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Se-myeong Jang, Sang-hyun Han, Hyo-dong Ban
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Patent number: 8809993Abstract: A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions.Type: GrantFiled: February 21, 2013Date of Patent: August 19, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sei-lyn Kwak, Se-myeong Jang, Min-sung Kang, Yun-jae Lee, Hyeon-kyu Lee