Patents by Inventor Sen-Kuei HSU
Sen-Kuei HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11296067Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.Type: GrantFiled: September 15, 2020Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Ming-Hsien Tsai
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Patent number: 11249112Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.Type: GrantFiled: July 20, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Wei-Hsun Lin, Sen-Kuei Hsu, De-Jian Liu
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Publication number: 20210407914Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.Type: ApplicationFiled: June 29, 2020Publication date: December 30, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Chien-Chang Lin
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Publication number: 20210249372Abstract: A manufacturing method of a semiconductor package includes the following steps. Semiconductor chips are disposed on a carrier. The semiconductor chips are grouped in a plurality of package units. The semiconductor chips are encapsulated in an encapsulant to form a reconstructed wafer. A redistribution structure is formed on the encapsulant. The redistribution structure electrically connects the semiconductor chips within a same package unit of the plurality of package units. The individual package units are separated by cutting through the reconstructed wafer along scribe line regions. In the reconstructed wafer, the plurality of package units are arranged so as to balance the number of scribe line regions extending across opposite halves of the reconstructed wafer in a first direction with respect to the number of scribe line regions extending across opposite halves of the reconstructed wafer in a second direction perpendicular to the first direction.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Yi-Che Chiang
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Publication number: 20210242159Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.Type: ApplicationFiled: June 10, 2020Publication date: August 5, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Kuo-Lung Pan, Sen-Kuei Hsu, Tin-Hao Kuo, Yi-Yang Lei, Ying-Cheng Tseng, Chi-Hui Lai
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Publication number: 20210183760Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.Type: ApplicationFiled: March 1, 2021Publication date: June 17, 2021Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
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Publication number: 20210159185Abstract: A semiconductor package includes a die, through insulator vias, an encapsulant, and a pair of metallization layers. The through insulator vias are disposed beside the die. The encapsulant wraps the die and the through insulator vias. The pair of metallization layers is disposed on opposite sides of the encapsulant. One end of each through insulator via contacts one of the metallization layers and the other end of each through insulator via contacts the other metallization layer. The through insulator vias form at least one photonic crystal structure. A pair of the through insulator vias is separated along a first direction by a channel filled by the encapsulant. A width of the channel along the first direction is larger than a pitch of the photonic crystal structure along the first direction.Type: ApplicationFiled: November 26, 2019Publication date: May 27, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Sen-Kuei Hsu
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Patent number: 10937734Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.Type: GrantFiled: May 15, 2017Date of Patent: March 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
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Publication number: 20210043564Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Yi-Che Chiang
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Publication number: 20210043590Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan
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Publication number: 20200411499Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.Type: ApplicationFiled: September 15, 2020Publication date: December 31, 2020Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Ming-Hsien Tsai
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Patent number: 10872842Abstract: A semiconductor device including a chip package and an antenna package disposed on the chip package is provided. The chip package includes a semiconductor chip, an encapsulation enclosing the semiconductor chip, and a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip. The antenna package includes an antenna pattern electrically coupled to the chip package, and an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a ceramic element in contact with the redistribution structure and thermally dissipating a heat generated from the semiconductor chip.Type: GrantFiled: February 25, 2019Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Albert Wan, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Han-Ping Pu, Hsin-Yu Pan, Sen-Kuei Hsu
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Patent number: 10867882Abstract: A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.Type: GrantFiled: November 25, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Albert Wan, Chao-Wen Shih, Han-Ping Pu, Hsin-Yu Pan, Sen-Kuei Hsu
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Publication number: 20200373219Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.Type: ApplicationFiled: August 14, 2020Publication date: November 26, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sen-Kuei Hsu, Ching-Feng Yang, Hsin-Yu Pan, Kai-Chiang Wu, Yi-Che Chiang
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Patent number: 10840197Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.Type: GrantFiled: November 20, 2018Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan
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Publication number: 20200355737Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen
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Publication number: 20200348341Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Inventors: Mill-Jer WANG, Ching-Nen PENG, Hung-Chih LIN, Wei-Hsun LIN, Sen-Kuei HSU, De-Jian LIU
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Publication number: 20200350782Abstract: Wireless charging devices, methods of manufacture thereof, and methods of charging electronic devices are disclosed. In some embodiments, a wireless charging device includes a controller, a molding material disposed around the controller, and an interconnect structure disposed over the molding material and coupled to the controller. The wireless charging device includes a wireless charging coil coupled to the controller. The wireless charging coil comprises a first portion disposed in the interconnect structure and a second portion disposed in the molding material. The wireless charging coil is adapted to provide an inductance to charge an electronic device.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Inventors: Chen-Hua Yu, Chita Chuang, Chen-Shien Chen, Ming Hung Tseng, Sen-Kuei Hsu, Yu-Feng Chen, Yen-Liang Lin
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Patent number: 10818588Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.Type: GrantFiled: January 31, 2019Date of Patent: October 27, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Yi-Che Chiang
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Patent number: 10818651Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.Type: GrantFiled: January 29, 2019Date of Patent: October 27, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Ming-Hsien Tsai