Patents by Inventor Sen-Kuei HSU

Sen-Kuei HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9875972
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shou-Zen Chang, Chi-Ming Huang, Kai-Chiang Wu, Sen-Kuei Hsu, Hsin-Yu Pan, Han-Ping Pu, Albert Wan
  • Publication number: 20180019209
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 18, 2018
    Inventors: Shou-Zen CHANG, Chi-Ming HUANG, Kai-Chiang WU, Sen-Kuei HSU, Hsin-Yu PAN, Han-Ping PU, Albert WAN
  • Publication number: 20170250130
    Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.
    Type: Application
    Filed: May 15, 2017
    Publication date: August 31, 2017
    Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
  • Publication number: 20170149404
    Abstract: An integrated circuit (IC) die for electromagnetic band gap (EBG) noise suppression is provided. A power mesh and a ground mesh are stacked within a back end of line (BEOL) region overlying a semiconductor substrate, and an inductor is arranged over the power and ground meshes. The inductor comprises a plurality of inductor segments stacked upon one another and connected end to end to define a length of the inductor. A capacitor underlies the power and ground meshes, and is connected in series with the inductor. Respective terminals of the capacitor and the inductor are respectively coupled to the power and ground meshes. A method for manufacturing the IC die is also provided.
    Type: Application
    Filed: November 23, 2015
    Publication date: May 25, 2017
    Inventors: Ming Hsien Tsai, Chien-Min Lin, Fu-Lung Hsueh, Han-Ping Pu, Sa-Lly Liu, Sen-Kuei Hsu
  • Patent number: 9653406
    Abstract: An embodiment device package includes a semiconductor device die comprising a passivation layer at a top surface, a first conductive line over the passivation layer and electrically connected to the device die, and a second conductive line over the passivation layer and electrically connected to the device die. The first conductive line is thicker than the second conductive line, and the first conductive line and the second conductive line are formed in a same device package layer.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
  • Publication number: 20170104356
    Abstract: Wireless charging devices, methods of manufacture thereof, and methods of charging electronic devices are disclosed. In some embodiments, a wireless charging device includes a controller, a molding material disposed around the controller, and an interconnect structure disposed over the molding material and coupled to the controller. The wireless charging device includes a wireless charging coil coupled to the controller. The wireless charging coil comprises a first portion disposed in the interconnect structure and a second portion disposed in the molding material. The wireless charging coil is adapted to provide an inductance to charge an electronic device.
    Type: Application
    Filed: October 9, 2015
    Publication date: April 13, 2017
    Inventors: Chen-Hua Yu, Chita Chuang, Chen-Shien Chen, Ming Hung Tseng, Sen-Kuei Hsu, Yu-Feng Chen, Yen-Liang Lin
  • Publication number: 20160313372
    Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
    Type: Application
    Filed: April 28, 2016
    Publication date: October 27, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mill-Jer WANG, Ching-Nen PENG, Hung-Chih LIN, Wei-Hsun LIN, Sen-Kuei HSU, De-Jian LIU
  • Publication number: 20160307852
    Abstract: An embodiment device package includes a semiconductor device die comprising a passivation layer at a top surface, a first conductive line over the passivation layer and electrically connected to the device die, and a second conductive line over the passivation layer and electrically connected to the device die. The first conductive line is thicker than the second conductive line, and the first conductive line and the second conductive line are formed in a same device package layer.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 20, 2016
    Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
  • Patent number: 9406648
    Abstract: A semiconductor device includes a device die, a first power supply die, and a second power supply die different from the first power supply die. The device die includes a first circuit and a second circuit. The first power supply die is electrically coupled to the first circuit and configured to supply power for the first circuit. The second power supply die is electrically coupled to the second circuit and configured to supply power for the second circuit. The first and second power supply dies are attached to the device die, and overlap the device die in a thickness direction of the device die.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chuei-Tang Wang, Monsen Liu, Sen-Kuei Hsu, Chen-Hua Yu
  • Patent number: 9354254
    Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Wei-Hsun Lin, Sen-Kuei Hsu, De-Jian Liu
  • Publication number: 20160093588
    Abstract: A semiconductor device includes a device die, a first power supply die, and a second power supply die different from the first power supply die. The device die includes a first circuit and a second circuit. The first power supply die is electrically coupled to the first circuit and configured to supply power for the first circuit. The second power supply die is electrically coupled to the second circuit and configured to supply power for the second circuit. The first and second power supply dies are attached to the device die, and overlap the device die in a thickness direction of the device die.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 31, 2016
    Inventors: Chuei-Tang WANG, Monsen LIU, Sen-Kuei HSU, Chen-Hua YU
  • Publication number: 20150241507
    Abstract: A method is disclosed that includes the operations outlined below. For a plurality of dies on a test fixture, an antenna distance between each of first antennas of one of the dies and every one of first antennas of the other dies is determined. The dies are categorized into die groups, wherein the antenna distance between each of the first antennas of one of the dies in one of the die groups and every one of the first antennas of the other dies in the same one of the die groups is larger than an interference threshold. Test processes are sequentially performed on the die groups. Each of the test processes is performed according to signal transmissions between the first antennas and second antennas of the under-test device each positionally corresponds to one of the first antennas.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen
  • Publication number: 20140266273
    Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
    Type: Application
    Filed: April 18, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer WANG, Ching-Nen PENG, Hung-Chih LIN, Wei-Hsun LIN, Sen-Kuei HSU, De-Jian LIU