Abstract: A via-filling method of a TGV substrate includes steps: filling a plurality of metal balls into a plurality of vias of the TGV substrate; using a heating process to melt the plurality of metal balls to form a liquid-state metal; and cooling down the liquid-state metal to form a solid-state metal inside the plurality of vias. Because the method needn't use solvents or fluxes, the solid-state metal inside the plurality of vias have better electric conductivity.

Abstract: A bonding and transferring method for die package structures is provided, including providing a die package structure which has a positioning adhesive disposed thereon, and providing a vibration base having at least one cavity corresponding to the positioning adhesive. By alignment of the positioning adhesive and the cavity, the die package structure can be positioned into the vibration base. A target substrate is further provided and bonded with the vibration base having the die package structure disposed thereon through a metal material. And a laser process is then performed to melt the metal material. At last, the vibration base and the positioning adhesive are removed so the die package structure is successfully bonded and transferred onto the target substrate. By employing the proposed process method of the present invention, rapid mass transfer result is accomplished, and the packaging yield of vertical light emitting diode die package structures is optimized.

Abstract: A manufacturing method of a semiconductor structure is disclosed, which includes: an initial structure is provided; a filling layer covering a spacer is formed on the initial structure; a filling layer with a first preset thickness is removed at a high first etching rate through a first etching process, then a filling layer with a second preset thickness is removed at a low second etching rate through a second etching process, and the partial spacer is exposed; and the filling layer and the spacer are patterned.

Abstract: An over-current protection circuit for composite transistor devices is provided, connected between an input terminal and a load, and including: a control-terminal voltage-generation module whose output voltage varies with its input voltage when driven by a first voltage, wherein the output voltage of the control-terminal voltage-generation module serves as a control-terminal voltage; a composite transistor device, connected between the control-terminal voltage-generation module and the load, configured to conduct in response to the control-terminal voltage and a second voltage to generate an output current flowing through the load; and an over-current protection module, connected between the composite transistor device and the load, wherein when the output current of the composite transistor device exceeds a preset limit, a clamping voltage is applied to the composite transistor device by the over-current protection module to limit a current flowing through the composite transistor device, thereby limiting th

Abstract: An LED circuit board structure includes first color LEDs, second color LEDs, third color LEDs, integrated circuit chips, a carrier board, first P-type pads, first color pads, first testing wires and first connecting wires. One of the first P-type pads is disposed at a pixel-front-side-pattern region for mounting a first P-type electrode. One of the first color pads is disposed at the pixel-front-side-pattern region for mounting a first pin of the integrated circuit chip. The first color pad electrically connects to the first P-type pad. A first testing wire is disposed at the pixel-front-side-pattern region and extends from the first P-type pad or the first color pad. The first connecting wire electrically connects two first testing wires in adjacent two pixel-front-side-pattern regions in parallel.

Abstract: An LED circuit board structure includes first color LEDs, second color LEDs, third color LEDs, a carrier board, first testing wires, first connecting wires, second testing wires and second connecting wires. Each of the first testing wire is located at the carrier board and electrically connects two first color LEDs in a pixel-front-side-pattern region in parallel. The first connecting wire electrically connects two first testing wires in adjacent two pixel-front-side-pattern regions. Each of the second testing wire is located at the carrier board and electrically connects two second color LEDs in a pixel-front-side-pattern region in parallel. The second connecting wire electrically connects two second testing wires in adjacent two pixel-front-side-pattern regions.

Abstract: A magnetic LED die transferring device includes a substrate, a plurality of magnetic members and a vibrating mechanism. The substrate includes a plurality of die locating areas arranged in intervals, and each of the die locating areas includes a locating surface. Each of the magnetic members corresponds to each of the die locating areas and includes an alignment N-pole and an alignment S-pole. The vibrating mechanism is coupled to the substrate. The N-pole and the S-pole of each of the magnetic LED dice are used to be attracted by each of the alignment N-poles and each of the alignment S-poles, respectively, to allow each of the magnetic LED dice to be transferred and aligned to each of the die locating areas.

Abstract: A light-emitting diode packaging structure and a method for fabricating the same is disclosed. A semiconductor wafer is provided, which includes semiconductor substrates. Each semiconductor substrate is penetrated with a first through hole and three second through holes. An insulation layer is formed on the surface of each semiconductor substrate and the inner surfaces of the first through hole, the first sub-through hole, and the second sub-through hole. A patterned electrode layer is formed on the top surface of the semiconductor substrate. A conductive material covering the insulation layer is formed in the first through hole and the second through hole and electrically connected to the patterned electrode layer. Three light-emitting diodes are respectively formed in the first sub-through holes of the second through holes of each semiconductor substrate and respectively electrically connected to the conductive material within the second through holes.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.

Abstract: An over-current protection circuit for composite transistor devices is provided, connected between an input terminal and a load, and including: a control-terminal voltage-generation module whose output voltage varies with its input voltage when driven by a first voltage, wherein the output voltage of the control-terminal voltage-generation module serves as a control-terminal voltage; a composite transistor device, connected between the control-terminal voltage-generation module and the load, configured to conduct in response to the control-terminal voltage and a second voltage to generate an output current flowing through the load; and an over-current protection module, connected between the composite transistor device and the load, wherein when the output current of the composite transistor device exceeds a preset limit, a clamping voltage is applied to the composite transistor device by the over-current protection module to limit a current flowing through the composite transistor device, thereby limiting th

Abstract: A method for fabricating a vertical light-emitting diode includes: providing a growth substrate, wherein an epitaxial layer is formed on the growth substrate; forming a metal combined substrate on the epitaxial layer, wherein the metal combined substrate comprises two first metal layers and a second metal layer therebetween, one of the first metal layers is close to the epitaxial layer, and another of the first metal layers is far away from the epitaxial layer; removing the growth substrate; forming a contact metal layer on the epitaxial layer; and removing the second metal layer and the first metal layer far away from the epitaxial layer and leaving the first metal layer close to the epitaxial layer. The vertical light-emitting diode, fabricated by the method, has a thinner thickness, a stronger mechanical strength, a higher light intensity, and a better heat-dissipating effect.

Abstract: The display device includes a substrate, a patterned wall, the first, second, third sub-pixels, and an optical layer. The patterned wall is disposed on the substrate and has a plurality of openings. The first sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The second sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The third sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer, wherein a first distance between a top surface of the light-emitting element and a top surface of the patterned wall is about 10 um to about 100 um. The optical layer is disposed on the patterned wall and in direct contact with at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

Abstract: An alignment module and alignment method for transferring magnetic light-emitting die are provided, including a backplane having at least one cavity, a magnetic pull device and magnetic light-emitting die. The magnetic pull device is located below the cavity and disposed correspondingly to the cavity. The magnetic light-emitting die includes a magnetic metallic substrate and a peripheral electrode formed on the magnetic metallic substrate. The peripheral electrode is surrounding on the magnetic metallic substrate and formed adjacent to an inner edge of the magnetic metallic substrate. Depth of the cavity is designed as equal to a thickness of the magnetic metallic substrate such that the die is accommodated and aligning transferred to the backplane by using the cavity and magnetic pull device. By employing the proposed die alignment techniques, accurate alignment result is achieved and thereby the present invention is applied perfectly for industrial mass transfer technology.

Abstract: A light-emitting diode packaging structure and a method for fabricating the same is disclosed. A semiconductor wafer is provided, which includes semiconductor substrates. Each semiconductor substrate is penetrated with a first through hole and three second through holes. An insulation layer is formed on the surface of each semiconductor substrate and the inner surfaces of the first through hole, the first sub-through hole, and the second sub-through hole. A patterned electrode layer is formed on the top surface of the semiconductor substrate. A conductive material covering the insulation layer is formed in the first through hole and the second through hole and electrically connected to the patterned electrode layer. Three light-emitting diodes are respectively formed in the first sub-through holes of the second through holes of each semiconductor substrate and respectively electrically connected to the conductive material within the second through holes.

Abstract: An alignment module and alignment method for transferring magnetic light-emitting die are provided, including a backplane having at least one cavity, a magnetic pull device and magnetic light-emitting die. The magnetic pull device is located below the cavity and disposed correspondingly to the cavity. The magnetic light-emitting die includes a magnetic metallic substrate and a peripheral electrode formed on the magnetic metallic substrate. The peripheral electrode is surrounding on the magnetic metallic substrate and formed adjacent to an inner edge of the magnetic metallic substrate. Depth of the cavity is designed as equal to a thickness of the magnetic metallic substrate such that the die is accommodated and aligning transferred to the backplane by using the cavity and magnetic pull device. By employing the proposed die alignment techniques, accurate alignment result is achieved and thereby the present invention is applied perfectly for industrial mass transfer technology.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.

Abstract: The present disclosure provides a binary weighted current source and a digital-to-analog converter, which include: a driving voltage generating circuit, generating a driving voltage based on a preset current; a current dividing circuit, connected to an output terminal of the driving voltage generating circuit; a current steering circuit, connected to the current dividing circuit. The current dividing circuit divides the driving voltage through resistors in series, and drives each of a plurality of current output transistors to output a current in response to a voltage across the current output transistor. Currents output by the plurality of current output transistor are binary weighted currents, each two of the binary weighted currents have a binary relationship, and the binary weighted currents are produced by successive binary divisions of the preset current.

Abstract: The present disclosure provides a binary weighted current source and a digital-to-analog converter, which include: a driving voltage generating circuit, generating a driving voltage based on a preset current; a current dividing circuit, connected to an output terminal of the driving voltage generating circuit; a current steering circuit, connected to the current dividing circuit. The current dividing circuit divides the driving voltage through resistors in series, and drives each of a plurality of current output transistors to output a current in response to a voltage across the current output transistor. Currents output by the plurality of current output transistor are binary weighted currents, each two of the binary weighted currents have a binary relationship, and the binary weighted currents are produced by successive binary divisions of the preset current.

Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.

Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.