Abstract: A method for fabricating a vertical light-emitting diode includes: providing a growth substrate, wherein an epitaxial layer is formed on the growth substrate; forming a metal combined substrate on the epitaxial layer, wherein the metal combined substrate comprises two first metal layers and a second metal layer therebetween, one of the first metal layers is close to the epitaxial layer, and another of the first metal layers is far away from the epitaxial layer; removing the growth substrate; forming a contact metal layer on the epitaxial layer; and removing the second metal layer and the first metal layer far away from the epitaxial layer and leaving the first metal layer close to the epitaxial layer. The vertical light-emitting diode, fabricated by the method, has a thinner thickness, a stronger mechanical strength, a higher light intensity, and a better heat-dissipating effect.

Abstract: The display device includes a substrate, a patterned wall, the first, second, third sub-pixels, and an optical layer. The patterned wall is disposed on the substrate and has a plurality of openings. The first sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The second sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The third sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer, wherein a first distance between a top surface of the light-emitting element and a top surface of the patterned wall is about 10 um to about 100 um. The optical layer is disposed on the patterned wall and in direct contact with at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

Abstract: An alignment module and alignment method for transferring magnetic light-emitting die are provided, including a backplane having at least one cavity, a magnetic pull device and magnetic light-emitting die. The magnetic pull device is located below the cavity and disposed correspondingly to the cavity. The magnetic light-emitting die includes a magnetic metallic substrate and a peripheral electrode formed on the magnetic metallic substrate. The peripheral electrode is surrounding on the magnetic metallic substrate and formed adjacent to an inner edge of the magnetic metallic substrate. Depth of the cavity is designed as equal to a thickness of the magnetic metallic substrate such that the die is accommodated and aligning transferred to the backplane by using the cavity and magnetic pull device. By employing the proposed die alignment techniques, accurate alignment result is achieved and thereby the present invention is applied perfectly for industrial mass transfer technology.

Abstract: A light-emitting diode packaging structure and a method for fabricating the same is disclosed. A semiconductor wafer is provided, which includes semiconductor substrates. Each semiconductor substrate is penetrated with a first through hole and three second through holes. An insulation layer is formed on the surface of each semiconductor substrate and the inner surfaces of the first through hole, the first sub-through hole, and the second sub-through hole. A patterned electrode layer is formed on the top surface of the semiconductor substrate. A conductive material covering the insulation layer is formed in the first through hole and the second through hole and electrically connected to the patterned electrode layer. Three light-emitting diodes are respectively formed in the first sub-through holes of the second through holes of each semiconductor substrate and respectively electrically connected to the conductive material within the second through holes.

Abstract: An alignment module and alignment method for transferring magnetic light-emitting die are provided, including a backplane having at least one cavity, a magnetic pull device and magnetic light-emitting die. The magnetic pull device is located below the cavity and disposed correspondingly to the cavity. The magnetic light-emitting die includes a magnetic metallic substrate and a peripheral electrode formed on the magnetic metallic substrate. The peripheral electrode is surrounding on the magnetic metallic substrate and formed adjacent to an inner edge of the magnetic metallic substrate. Depth of the cavity is designed as equal to a thickness of the magnetic metallic substrate such that the die is accommodated and aligning transferred to the backplane by using the cavity and magnetic pull device. By employing the proposed die alignment techniques, accurate alignment result is achieved and thereby the present invention is applied perfectly for industrial mass transfer technology.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.

Abstract: The present disclosure provides a binary weighted current source and a digital-to-analog converter, which include: a driving voltage generating circuit, generating a driving voltage based on a preset current; a current dividing circuit, connected to an output terminal of the driving voltage generating circuit; a current steering circuit, connected to the current dividing circuit. The current dividing circuit divides the driving voltage through resistors in series, and drives each of a plurality of current output transistors to output a current in response to a voltage across the current output transistor. Currents output by the plurality of current output transistor are binary weighted currents, each two of the binary weighted currents have a binary relationship, and the binary weighted currents are produced by successive binary divisions of the preset current.

Abstract: The present disclosure provides a binary weighted current source and a digital-to-analog converter, which include: a driving voltage generating circuit, generating a driving voltage based on a preset current; a current dividing circuit, connected to an output terminal of the driving voltage generating circuit; a current steering circuit, connected to the current dividing circuit. The current dividing circuit divides the driving voltage through resistors in series, and drives each of a plurality of current output transistors to output a current in response to a voltage across the current output transistor. Currents output by the plurality of current output transistor are binary weighted currents, each two of the binary weighted currents have a binary relationship, and the binary weighted currents are produced by successive binary divisions of the preset current.

Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.

Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.

Abstract: The display device includes a substrate, a patterned wall, the first, second, third sub-pixels, and an optical layer. The patterned wall is disposed on the substrate and has a plurality of openings. The first sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The second sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The third sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer, wherein a first distance between a top surface of the light-emitting element and a top surface of the patterned wall is about 10 um to about 100 um. The optical layer is disposed on the patterned wall and in direct contact with at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.

Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.

Abstract: A non-volatile memory includes a back gate, a first graphene ribbon layer, a dielectric layer, a second graphene ribbon layer and a porous dielectric layer. The back gate is disposed in a substrate. The first graphene ribbon layer is disposed on the substrate. The dielectric layer covers the first graphene ribbon layer but exposes an exposed part of the first graphene ribbon layer. The second graphene ribbon layer including two end parts connected by a cantilever part is disposed above the first graphene ribbon layer, and the cantilever part is right above the exposed part of the first graphene ribbon layer. The porous dielectric layer is disposed on the dielectric layer and seals the cantilever part. The present invention also provides a method of forming said non-volatile memory.

Abstract: A manufacturing method of a metal-insulator-metal (MIM) capacitor structure includes the following steps. A bottom plate is formed. A first conductive layer is patterned to be the bottom plate, and the first conductive layer includes a metal element. An interface layer is formed on the first conductive layer by performing a nitrous oxide (N2O) treatment on a top surface of the first conductive layer. The interface layer includes oxygen and the metal element of the first conductive layer. A dielectric layer is formed on the interface layer. A top plate is formed on the dielectric layer. The metal-insulator-metal capacitor structure includes the bottom plate, the interface layer disposed on the bottom plate, the dielectric layer disposed on the interface layer, and the top plate disposed on the dielectric layer.

Abstract: The present disclosure relates to semiconductors and low dropout regulator (LDO) circuits. A LDO circuit may include first and second adjustment pipes and first and second error amplifiers. When an output voltage outputted by the output end of the LDO circuit is smaller than a reference voltage, the first error amplifier controls the first adjustment pipe to be turned on, and the second error amplifier controls the second adjustment pipe to be turned off. Alternative, when the output voltage is greater than the reference voltage, the first error amplifier controls the first adjustment pipe to be turned off, and the second error amplifier controls the second adjustment pipe to be turned on.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a low dropout regulator (LDO) circuit. The LDO circuit includes a first adjustment pipe, a second adjustment pipe, a first error amplifier, and a second error amplifier. The first adjustment pipe is connected between an input end and an output end of the LDO circuit. The second adjustment pipe is connected between the output end of the LDO circuit and the ground. The first error amplifier includes a first input end and a second input end, where the first input end is connected to the output end of the LDO circuit, and the second input end is used to receive a reference voltage. The second error amplifier includes a third input end and a fourth input end, where the third input end is connected to the output end of the LDO circuit, and the fourth input end is used to receive the reference voltage.

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

Abstract: A phosphor, having a general formula of K2[Si1-xGex]yF6:Mn1-y4+. The phosphor is excited to emit a light having a first main emission peak with a first maximum emission intensity and a first dominant wavelength, wherein a relative emission intensity S of the light of the phosphor is constantly greater than 85% across an temperature of the phosphor between 300 K and 470 K during operation, wherein S=(IT/IRT)*100%, IRT and IT are the first maximum emission intensity when the temperature of the phosphor is at 300 K and T during operation respectively, and 300 K<T?470K.

Abstract: This invention involves a method and a device for enhanced oil-water separation and desalination in a low-pressure separator. The water-containing oil is mixed with desalted water in a countercurrent way at the entrance, wherein the desalted water accounts for 0-1% of the water-containing oil by volume. The resultant oil-water mixture then enters a T-shaped liquid-gas separator (3) for degassing treatment to quickly separate gas from the mixture. In a low-pressure separator, the oil-water mixture flows, from left to right, to a flow conditioner (4) to uniformly distribute the mixture in the transverse section, and then flows to a hydrophilic droplet agglomeration module (5) and a CPI fast separation module (6) to separate water from oil, wherein part of the separated water is discharged and the oil with a trace of water (0-0.01%) passes over a partition (18) to a deep separation segment.