Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.

Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.

Abstract: The display device includes a substrate, a patterned wall, the first, second, third sub-pixels, and an optical layer. The patterned wall is disposed on the substrate and has a plurality of openings. The first sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The second sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The third sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer, wherein a first distance between a top surface of the light-emitting element and a top surface of the patterned wall is about 10 um to about 100 um. The optical layer is disposed on the patterned wall and in direct contact with at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.

Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.

Abstract: A non-volatile memory includes a back gate, a first graphene ribbon layer, a dielectric layer, a second graphene ribbon layer and a porous dielectric layer. The back gate is disposed in a substrate. The first graphene ribbon layer is disposed on the substrate. The dielectric layer covers the first graphene ribbon layer but exposes an exposed part of the first graphene ribbon layer. The second graphene ribbon layer including two end parts connected by a cantilever part is disposed above the first graphene ribbon layer, and the cantilever part is right above the exposed part of the first graphene ribbon layer. The porous dielectric layer is disposed on the dielectric layer and seals the cantilever part. The present invention also provides a method of forming said non-volatile memory.

Abstract: A manufacturing method of a metal-insulator-metal (MIM) capacitor structure includes the following steps. A bottom plate is formed. A first conductive layer is patterned to be the bottom plate, and the first conductive layer includes a metal element. An interface layer is formed on the first conductive layer by performing a nitrous oxide (N2O) treatment on a top surface of the first conductive layer. The interface layer includes oxygen and the metal element of the first conductive layer. A dielectric layer is formed on the interface layer. A top plate is formed on the dielectric layer. The metal-insulator-metal capacitor structure includes the bottom plate, the interface layer disposed on the bottom plate, the dielectric layer disposed on the interface layer, and the top plate disposed on the dielectric layer.

Abstract: The present disclosure relates to semiconductors and low dropout regulator (LDO) circuits. A LDO circuit may include first and second adjustment pipes and first and second error amplifiers. When an output voltage outputted by the output end of the LDO circuit is smaller than a reference voltage, the first error amplifier controls the first adjustment pipe to be turned on, and the second error amplifier controls the second adjustment pipe to be turned off. Alternative, when the output voltage is greater than the reference voltage, the first error amplifier controls the first adjustment pipe to be turned off, and the second error amplifier controls the second adjustment pipe to be turned on.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a low dropout regulator (LDO) circuit. The LDO circuit includes a first adjustment pipe, a second adjustment pipe, a first error amplifier, and a second error amplifier. The first adjustment pipe is connected between an input end and an output end of the LDO circuit. The second adjustment pipe is connected between the output end of the LDO circuit and the ground. The first error amplifier includes a first input end and a second input end, where the first input end is connected to the output end of the LDO circuit, and the second input end is used to receive a reference voltage. The second error amplifier includes a third input end and a fourth input end, where the third input end is connected to the output end of the LDO circuit, and the fourth input end is used to receive the reference voltage.

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

Abstract: A phosphor, having a general formula of K2[Si1-xGex]yF6:Mn1-y4+. The phosphor is excited to emit a light having a first main emission peak with a first maximum emission intensity and a first dominant wavelength, wherein a relative emission intensity S of the light of the phosphor is constantly greater than 85% across an temperature of the phosphor between 300 K and 470 K during operation, wherein S=(IT/IRT)*100%, IRT and IT are the first maximum emission intensity when the temperature of the phosphor is at 300 K and T during operation respectively, and 300 K<T?470K.

Abstract: This invention involves a method and a device for enhanced oil-water separation and desalination in a low-pressure separator. The water-containing oil is mixed with desalted water in a countercurrent way at the entrance, wherein the desalted water accounts for 0-1% of the water-containing oil by volume. The resultant oil-water mixture then enters a T-shaped liquid-gas separator (3) for degassing treatment to quickly separate gas from the mixture. In a low-pressure separator, the oil-water mixture flows, from left to right, to a flow conditioner (4) to uniformly distribute the mixture in the transverse section, and then flows to a hydrophilic droplet agglomeration module (5) and a CPI fast separation module (6) to separate water from oil, wherein part of the separated water is discharged and the oil with a trace of water (0-0.01%) passes over a partition (18) to a deep separation segment.

Abstract: The present invention relates to a medicament design pocket of ODC. Based on the crystal structure of human ODC, the binding site area of putrescine and PLP ligand on the ODC homodimer interface is the medicament pocket, which is used for screening or designing or modifying inhibitors of human ODC, or screening or designing or modifying inhibitors of non-human ODC, or screening or designing or modifying protein inhibitor highly homologous to the binding site of putrescine and pyridoxal phosphate on the interface of ODC homodimer. The invention also provides the structure of the inhibitor and its application thereof. The technical solutions in the invention provide reliable theoretical basis for the research and development of human ODC, the prevention, treatment and diagnosis of tumors and pathogenic microbial infections, and the research and development and preparation of medicaments for the treatment of tumors or pathogenic microbial infections.

Abstract: An embodiment of the present disclosure discloses a phosphor material and a manufacturing method thereof. The general composition of the phosphor material is A2-xMO4:Eux, wherein A includes a single element or at least two elements selected from the group consisting of Ca, Sr, and Ba, M is Si, Ge or combination thereof, wherein x is greater than 0.01 and 2-x>0. The phosphor material can be excited by a first excitation wavelength and emit a first emission spectrum and, excited by a second excitation wavelength and emit a second emission spectrum. The first excitation wavelength is different from the second excitation wavelength, and the first emission spectrum is different from the second emission spectrum.

Abstract: An optical electrical device comprises a base and a transparent conductive structure on the base is disclosed. The base further comprises a light-emitting device and the transparent conductive structure comprises a transparent conductive oxide layer and a passivation layer on the transparent conductive oxide layer. The material of the transparent conductive oxide layer comprises transparent conductive metal oxide, such as ZnO. Furthermore, the transparent conductive metal oxide also comprises impurities, such as a carrier e.g. gallium.

Abstract: A phosphor, having a general formula of K2[Si1-xGex]yF6:Mn1-y4+. The phosphor is excited to emit a light having a first main emission peak with a first maximum emission intensity and a first dominant wavelength, wherein a relative emission intensity S of the light of the phosphor is constantly greater than 85% across an temperature of the phosphor between 300 K and 470 K during operation, wherein S=(IT/IRT)*100%, IRT and IT are the first maximum emission intensity when the temperature of the phosphor is at 300 K and T during operation respectively, and 300 K<T?470K.

Abstract: A thin-film deposition apparatus comprises a chamber; a carrier in the chamber; a showerhead on the carrier, wherein the showerhead comprises multiple first gas-dispensing holes, multiple second gas-dispensing holes and multiple plasma-generating portions; and a first gas inlet system for providing a first process gas, wherein the first process gas outputted from the multiple first gas-dispensing holes.

Abstract: A method of fabricating an epitaxial device, comprising: providing a substrate having a first surface and a normal direction; epitaxially forming a first transition layer in a first temperature on the first surface of the substrate and in-situ incorporating a porogen into the first transition layer; and adjusting the first temperature to a second temperature to burn out the porogen from the first transition layer to form a hollow component inside the first transition layer.

Abstract: A curable liquid formulation comprising: (i) one or more near-infrared absorbing polymethine dyes; (ii) one or more crosslinkable polymers; and (iii) one or more casting solvents. The invention is also directed to solid near-infrared absorbing films composed of crosslinked forms of the curable liquid formulation. The invention is also directed to a microelectronic substrate containing a coating of the solid near-infrared absorbing film as well as a method for patterning a photoresist layer coated on a microelectronic substrate in the case where the near-infrared absorbing film is between the microelectronic substrate and a photoresist film.

Abstract: Techniques for organizing and presenting deals/commercial offers received by users in emails are provided. Emails directed to a user that contain commercial offers for the user are determined. The determined emails are stored in a deal folder for the user. A deal newsletter is generated that at least summarizes commercial offers contained in at least a portion of the emails stored in the deal folder. The deal folder may be displayed to show the user the received deal emails. Furthermore, the deal newsletter may be displayed to the user to summarize the received deals for the user.