Patents by Inventor Seng Guan Chow

Seng Guan Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7812449
    Abstract: An integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and forming a re-routing film over the encapsulant, the base device, and the base interconnect for connectivity without a substrate.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: October 12, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Heap Hoe Kuan, Seng Guan Chow, Rui Huang
  • Publication number: 20100244277
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a sacrificial carrier assembly having a stack interconnector thereover; mounting an integrated circuit having a connector over the sacrificial carrier assembly with the connector over the stack interconnector; dispensing an underfill material between the sacrificial carrier assembly and the integrated circuit with the underfill material substantially free of a void; encapsulating the integrated circuit over the sacrificial carrier assembly and the underfill material; exposing the stack interconnector by removing the sacrificial carrier assembly; and forming a base array over the underfill material and the stack interconnector.
    Type: Application
    Filed: March 25, 2009
    Publication date: September 30, 2010
    Inventors: Rui Huang, Heap Hoe Kuan, Yaojian Lin, Seng Guan Chow
  • Publication number: 20100244216
    Abstract: A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.
    Type: Application
    Filed: March 24, 2009
    Publication date: September 30, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Rui Huang, Heap Hoe Kuan, Yaojian Lin, Seng Guan Chow
  • Publication number: 20100233852
    Abstract: A semiconductor device has a plurality of similar sized semiconductor die each with a plurality of bond pads formed over a surface of the semiconductor die. An insulating layer is formed around a periphery of each semiconductor die. A plurality of conductive THVs is formed through the insulating layer. A plurality of conductive traces is formed over the surface of the semiconductor die electrically connected between the bond pads and conductive THVs. The semiconductor die are stacked to electrically connect the conductive THVs between adjacent semiconductor die. The stacked semiconductor die are mounted within an integrated cavity of a substrate or leadframe structure. An encapsulant is deposited over the substrate or leadframe structure and the semiconductor die. A thermally conductive lid is formed over a surface of the substrate or leadframe structure. The stacked semiconductor die are attached to the thermally conductive lid.
    Type: Application
    Filed: May 27, 2010
    Publication date: September 16, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
  • Publication number: 20100230806
    Abstract: A semiconductor device is made by forming a plurality of conductive pillars vertically over a temporary carrier. A conformal insulating layer is formed over the conductive pillars. A conformal conductive layer is formed over the conformal insulating layer. A first conductive pillar, conformal insulating layer, and conformal conductive layer constitute a vertically oriented integrated capacitor. A semiconductor die or component is mounted over the carrier. An encapsulant is deposited over the semiconductor die or component and around the conformal conductive layer. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure includes an integrated passive device. The first interconnect structure is electrically connected to the semiconductor die or component and vertically oriented integrated capacitor. The carrier is removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first side of the encapsulant.
    Type: Application
    Filed: March 13, 2009
    Publication date: September 16, 2010
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Rui Huang, Heap Hoe Kuan, Yaojian Lin, Seng Guan Chow
  • Patent number: 7795078
    Abstract: A cavity semiconductor package has a pre-molded leadframe construction. The leadframe is formed by molding around a die pad, and plural terminal lands. The leadframe has a hole for an acoustic port, such that the package can be soldered on a back side of a printed circuit board and have air access to a sensor die in the package from a front side of the printed circuit board via the acoustic port. The leadframe may also have a hollow or concave recess that defines an acoustic cavity in conjunction with the sensor die or printed circuit board.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: September 14, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Kambhampati Ramakrishna, Seng Guan Chow
  • Publication number: 20100224974
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a component side and a system side; depositing a solder resist layer on the component side of the package substrate; patterning groups of access openings and a die mount opening in the solder resist layer; attaching an integrated circuit die in the die mount opening; forming conductive contacts in the access openings; and attaching system interconnects to the system side of the package substrate including controlling a coplanarity of the system interconnects by the solder resist layer.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 9, 2010
    Inventors: Il Kwon Shim, Seng Guan Chow, Heap Hoe Kuan
  • Publication number: 20100224978
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a device to the substrate; providing interconnects on the substrate; and forming a flexible tape substantially conformal to the device and contacting the interconnects.
    Type: Application
    Filed: March 3, 2010
    Publication date: September 9, 2010
    Inventors: Il Kwon Shim, Seng Guan Chow, Heap Hoe Kuan
  • Patent number: 7790504
    Abstract: An integrated circuit package system is provided providing a first structure, forming a compression via in the first structure, forming a stud bump on a second structure and pressing the stud bump into the compression via forming a mechanical bond.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: September 7, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Kambhampati Ramakrishna, Byung Joon Han, Seng Guan Chow
  • Publication number: 20100219523
    Abstract: A stackable integrated circuit package system includes: a substrate having a first side and a second side opposite the first side, the substrate having a cavity provided therein; a first integrated circuit die in the cavity with a first interconnect extending out from the cavity without connection and a second interconnect connected to the first side; a first mold compound to cover the first integrated circuit die, the second interconnect, and a portion of the first interconnect; a second integrated circuit die mounted to the first integrated circuit die with a third interconnect connected to the second side; a second mold compound to cover the second integrated circuit die and the third interconnect; and external interconnects, not encapsulated by the second encapsulant, mounted on the second side.
    Type: Application
    Filed: May 10, 2010
    Publication date: September 2, 2010
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Dioscoro A. Merilo, Antonio B. Dimaano, JR.
  • Patent number: 7786593
    Abstract: An integrated circuit die is provided having a body portion having a singulation side and a pedestal portion extending from the body portion and having a singulation side coplanar with the singulation side of the body portion.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: August 31, 2010
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Virgil Cotoco Ararao, Il Kwon Shim, Seng Guan Chow
  • Patent number: 7786008
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a silicon substrate having a circuitry layer; creating a partial via through the circuitry layer; filling the partial via with a plug having a bottom surface; creating a recess that is angled outward and exposes the bottom surface of the plug; and coating the recess with a recess-insulation-layer while leaving the bottom surface of the plug exposed.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: August 31, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Seng Guan Chow, Seung Uk Yoon
  • Patent number: 7781261
    Abstract: An integrated circuit package system includes: mounting a device structure in an offset location over a carrier with the device structure having a bond pad and a contact pad; connecting an electrical interconnect between the bond pad and the carrier; forming an anti-flash structure over the device structure with the anti-flash structure exposing the contact pad; and forming a package encapsulation adjacent to the anti-flash structure and over the carrier.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: August 24, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua
  • Publication number: 20100193931
    Abstract: A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.
    Type: Application
    Filed: April 9, 2010
    Publication date: August 5, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
  • Patent number: 7768125
    Abstract: A chip package system is provided including providing a chip having interconnects provided thereon; forming a molding compound on the chip and encapsulating the interconnects; and forming a recess in the molding compound above the interconnects to expose the interconnects.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: August 3, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Heap Hoe Kuan
  • Patent number: 7767496
    Abstract: A semiconductor device is made by first forming a protective layer over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: August 3, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Il Kwon Shim, Yaojian Lin, Seng Guan Chow
  • Publication number: 20100176497
    Abstract: An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height.
    Type: Application
    Filed: March 23, 2010
    Publication date: July 15, 2010
    Inventors: Dioscoro A. Merilo, Heap Hoe Kuan, You Yang Ong, Seng Guan Chow, Ma. Shirley Asoy
  • Patent number: 7750452
    Abstract: A semiconductor package includes a substrate or leadframe structure. A plurality of interconnected dies, each incorporating a plurality of through-hole vias (THVs) disposed along peripheral surfaces of the plurality of dies, are disposed over the substrate or leadframe structure. The plurality of THVs are coupled to a plurality of bond pads through a plurality of a metal traces. A top surface of a first THV is coupled to a bottom surface of a second THV. An encapsulant is formed over a portion of the substrate or leadframe structure and the plurality of dies.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: July 6, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
  • Patent number: 7746656
    Abstract: An offset integrated circuit package-on-package stacking system is provided including providing a base substrate, providing an array of contact pads on the base substrate, mounting an active component and an optional passive component on the base substrate, injecting a mold cap on the base substrate, mounting an offset package on the base substrate and the mold cap, and singulating a package-on-package from the base substrate.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: June 29, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Byung Joon Han, Seng Guan Chow
  • Publication number: 20100155926
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a substrate including: patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.
    Type: Application
    Filed: March 2, 2010
    Publication date: June 24, 2010
    Inventors: Byung Tai Do, Il Kwon Shim, Seng Guan Chow