Patents by Inventor Seok Cheon Baek
Seok Cheon Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11903206Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.Type: GrantFiled: May 18, 2022Date of Patent: February 13, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Seon Ahn, Ji Sung Cheon, Young Jin Kwon, Seok Cheon Baek, Woong Seop Lee
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Patent number: 11882701Abstract: A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.Type: GrantFiled: May 28, 2021Date of Patent: January 23, 2024Assignee: Samsung Electronics Co., Ltd.Inventor: Seok Cheon Baek
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Patent number: 11791287Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.Type: GrantFiled: August 31, 2021Date of Patent: October 17, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Geun Won Lim, Seok Cheon Baek, Ji Sung Cheon, Jong Woo Shin, Bong Hyun Choi
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Publication number: 20230189524Abstract: A semiconductor memory device may include a substrate including a first and a second block region, and a stacked structure including insulating films and gate electrodes alternately stacked on the substrate. A vertical channel structure, a word line cut structure, and a block cut structure may penetrate the stacked structure. The word line cut structure may extend in a second direction. The block cut structure may extend in a first direction, connect to the word line cut structure, and define the first and second block regions. The block cut structure may include a first portion connected to the word line cut structure and a second portion connected to the first portion. From a planar viewpoint, the first portion may include at least a part not overlapping the second portion in the first direction and at least a region not overlapping the word line cut structure in the first direction.Type: ApplicationFiled: August 10, 2022Publication date: June 15, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Min Gu KANG, Sang Don ZOO, Joon Sung KIM, Junghwan PARK, Seorim MOON, Seok Cheon BAEK, Cheol RYOU, Sun Young LEE, Cheol-Min LIM
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Patent number: 11678485Abstract: A vertical memory device, including: a substrate including a cell array region and an extension region; gate electrodes stacked on each other with a plurality of levels, wherein each of the gate electrodes includes a pad, and wherein the pads disposed on the gate electrodes form at least one staircase structure on the extension region of the substrate; a channel extending in a first direction on the cell array region of the substrate through at least one of the gate electrodes; and dummy gate electrode groups disposed on the extension region of the substrate, wherein the dummy gate electrode groups includes dummy gate electrodes, wherein each of the dummy gate electrodes are spaced apart from a corresponding gate electrode among the gate electrodes stacked at a same level, wherein the dummy gate electrode groups are spaced apart from each other in a second direction.Type: GrantFiled: January 20, 2020Date of Patent: June 13, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Seok-Cheon Baek
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Patent number: 11626421Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.Type: GrantFiled: March 9, 2021Date of Patent: April 11, 2023Inventor: Seok Cheon Baek
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Patent number: 11495495Abstract: A method of manufacturing a semiconductor device includes forming a base layer on a substrate. A structure layer is Conned on the base layer. The structure layer includes at least one material layer. A structure pattern is formed on the base layer. The structure pattern includes a first trench extending in a first direction and a second trench having a cross portion extending in a second direction that is perpendicular to the first direction. The second trench is connected to the first trench. The structure pattern further includes a base pattern having a recess portion recessed downward from a surface of the base layer at the cross portion of the second trench.Type: GrantFiled: October 1, 2020Date of Patent: November 8, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Geun-Won Lim, Myung-Keun Lee, Seok-Cheon Baek, Kyeong-Jin Park
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Patent number: 11476265Abstract: A three-dimensional semiconductor device comprises a stack structure on a lower structure, a vertical channel structure passing through the stack structure, and a first vertical support structure passing through the stack structure and spaced apart from the vertical channel structure. The stack structure includes interlayer insulation layers and gate horizontal patterns, alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure. The vertical channel structure and the first vertical support structure have different cross-sectional shapes. The vertical channel structure further includes a channel semiconductor layer. The vertical channel structure includes first and second vertical regions, and a width variation portion between the first and second vertical regions. The interlayer insulation layers include an intermediate interlayer insulation layer adjacent to the width variation portion.Type: GrantFiled: May 2, 2019Date of Patent: October 18, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Seok Cheon Baek
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Publication number: 20220278125Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.Type: ApplicationFiled: May 18, 2022Publication date: September 1, 2022Inventors: Jong Seon AHN, Ji Sung CHEON, Young Jin KWON, Seok Cheon BAEK, Woong Seop LEE
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Patent number: 11398491Abstract: A three-dimensional semiconductor device comprises a stack structure on a lower structure, a vertical channel structure passing through the stack structure, and a first vertical support structure passing through the stack structure and spaced apart from the vertical channel structure. The stack structure includes interlayer insulation layers and gate horizontal patterns, alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure. The vertical channel structure and the first vertical support structure have different cross-sectional shapes. The vertical channel structure further includes a channel semiconductor layer. The vertical channel structure includes first and second vertical regions, and a width variation portion between the first and second vertical regions. The interlayer insulation layers include an intermediate interlayer insulation layer adjacent to the width variation portion.Type: GrantFiled: August 16, 2021Date of Patent: July 26, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Seok Cheon Baek
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Patent number: 11342351Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.Type: GrantFiled: January 25, 2019Date of Patent: May 24, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Seon Ahn, Ji Sung Cheon, Young Jin Kwon, Seok Cheon Baek, Woong Seop Lee
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Patent number: 11322510Abstract: A vertical memory device includes a gate structure including a first gate electrode on a peripheral circuit region of a substrate, the substrate containing a cell region and the peripheral circuit region, a plurality of second gate electrodes sequentially stacked on the cell region of the substrate, the plurality of second gate electrodes spaced apart from each other in a vertical direction to an upper surface of the substrate, a channel extending in the vertical direction on the cell region of the substrate and extending through at least one of the second gate electrodes, and a first insulating interlayer covering the gate structure on the peripheral circuit region of the substrate, a cross-section in one direction of an upper surface of a portion of the first insulating interlayer overlapping the gate structure in the vertical direction having a shape of a portion of a polygon.Type: GrantFiled: September 30, 2020Date of Patent: May 3, 2022Assignee: Samsung Electronics Co.. Ltd.Inventors: Ji-Sung Cheon, Seok-Cheon Baek
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Publication number: 20220130851Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first, block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.Type: ApplicationFiled: January 5, 2022Publication date: April 28, 2022Inventors: Jun Hyoung KIM, Kwang Soo KIM, Seok Cheon BAEK, Geun Won LIM
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Patent number: 11264401Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.Type: GrantFiled: February 7, 2019Date of Patent: March 1, 2022Inventors: Jun Hyoung Kim, Kwang Soo Kim, Seok Cheon Baek, Geun Won Lim
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Publication number: 20210398915Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.Type: ApplicationFiled: August 31, 2021Publication date: December 23, 2021Inventors: Geun Won Lim, Seok Cheon Baek, Ji Sung Cheon, Jong Woo Shin, Bong Hyun Choi
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Publication number: 20210375904Abstract: A three-dimensional semiconductor device comprises a stack structure on a lower structure, a vertical channel structure passing through the stack structure, and a first vertical support structure passing through the stack structure and spaced apart from the vertical channel structure. The stack structure includes interlayer insulation layers and gate horizontal patterns, alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure. The vertical channel structure and the first vertical support structure have different cross-sectional shapes. The vertical channel structure further includes a channel semiconductor layer. The vertical channel structure includes first and second vertical regions, and a width variation portion between the first and second vertical regions. The interlayer insulation layers include an intermediate interlayer insulation layer adjacent to the width variation portion.Type: ApplicationFiled: August 16, 2021Publication date: December 2, 2021Applicant: Samsung Electronics Co., Ltd.Inventor: Seok Cheon BAEK
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Patent number: 11145672Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.Type: GrantFiled: December 7, 2019Date of Patent: October 12, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Cheon Baek, Boh Chang Kim, Chung Ki Min, Ji Hoon Park, Byung Kwan You
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Patent number: 11133267Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.Type: GrantFiled: December 20, 2018Date of Patent: September 28, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Geun Won Lim, Seok Cheon Baek, Ji Sung Cheon, Jong Woo Shin, Bong Hyun Choi
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Publication number: 20210288072Abstract: A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.Type: ApplicationFiled: May 28, 2021Publication date: September 16, 2021Applicant: Samsung Electronics Co., Ltd.Inventor: Seok Cheon BAEK
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Patent number: 11056502Abstract: A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.Type: GrantFiled: March 27, 2019Date of Patent: July 6, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Seok Cheon Baek