Abstract: A method for preventing generation of program disturbance incurred by hot electrons in a NAND flash memory device. A channel boosting disturb-prevention voltage lower than a program-prohibit voltage applied to other word lines is applied to edge word lines coupled to memory cells that are nearest to select transistors. As a result, an electric field between the memory cells coupled to the edge word lines and the select transistors is weakened, and the energy of the hot electrons is reduced.

Abstract: A method for preventing generation of program disturbance incurred by hot electrons in a NAND flash memory device. A channel boosting disturb-prevention voltage lower than a program-prohibit voltage applied to other word lines is applied to edge word lines coupled to memory cells that are nearest to select transistors. As a result, an electric field between the memory cells coupled to the edge word lines and the select transistors is weakened, and the energy of the hot electrons is reduced.

Abstract: The present invention relates to a flash memory device. The flash memory device comprises a first memory cell array having a plurality of first flash memory cells of which a gate of each cell of the plurality of first flash memory cells being connected to a respective first word line and a terminal of each cell of the plurality of first flash memory cells being connected to a respective first bit line; a plurality of switching parts each having first and second terminals, the first terminal of each switching part being connected to the respective first bit line; and a second flash memory cell array having a plurality of second flash memory cells of which a gate of each cell of the plurality of second flash memory cells being connected to a common second word line and a terminal of each cell of the plurality of second flash memory cells being connected to a respective second bit line; wherein the second terminals of the plurality of the switching parts are commonly connected to the common second word line.

Abstract: The present invention relates to a flash memory device. The flash memory device comprises a first flash memory cell array in which a plurality of flash memory cells are connected by a plurality of word lines and a plurality of bit lines, a plurality of switching means connected to bit lines of each of the flash memory cell array, and a second flash memory cell array in which a plurality of flash memory cells are connected by a plurality of word lines and a plurality of bit lines, and a common terminal of the plurality of the switching means and each of the word lines are connected. Therefore, the present invention can reduce the manufacturing cost of a product without increasing the chip size even though a self-converged erase mode is employed.

Abstract: The present invention relates to a flash memory device. The present invention relates to a flash memory device in which a capacitor of a given capacitance is connected between a bit line connected to a drain region and a ground line within a flash cell array, and method of erasing the same. Therefore, the present invention can reduce the time and power consumption in the cell erase operation, by accelerating an increase of hot carriers generated in a diode reverse-bias state between the drain region and a semiconductor substrate upon an erase operation of the cell to prevent over-erase or non-erase of the cell by means of hot carriers and by thus solving an over-erase problem of the cell without requiring additional pre-programming and verification operation and additional post-programming and verification operation.