Abstract: A semiconductor memory includes: a first line; a second line spaced apart from the first line and extending in a first direction; a third line spaced apart from the second line and extending in a second direction; a first memory cell disposed between the first and second lines at an intersection region of the first and second lines, the first memory cell including a first selection element layer, a first electrode, and a first insert electrode interposed between the first selection element layer and the first electrode; and a second memory cell disposed between the second and third lines at an intersection region of the second and third lines, the second memory cell including a second selection element layer, a second electrode, and a second insert electrode interposed between the second selection element layer and the second electrode.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory may include: a memory circuit comprising a plurality of memory cells; a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal.

Abstract: A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit suitable for generating a first write current at a first point of time corresponding to pre-write latency that is shorter than write latency and generating a second write current at a second point of time corresponding to the write latency, based on a write command signal, a write data signal, and a latency information signal, and a memory cell array suitable for storing a data value corresponding to the write data signal based on the first and second write currents.

Abstract: A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.

Abstract: An operating method of an electronic device including a semiconductor memory, the operating method includes selecting one of a plurality of memory cells during a set operation, applying a write current having a slow quenching pattern to the selected memory cell, monitoring a cell current flowing through the selected memory cell, generating a discharge control signal corresponding to a result of the monitoring, and discharging the write current in response to the discharge control signal.

Abstract: Disclosed is a vacuum cleaner including a flow path to guide air suctioned or discharged and a resonator connected to the flow path. The resonator is configured to change a resonance frequency to be canceled. Therefore, when the noise generated by changing operation modes of the vacuum cleaner is changed, the noise may be cancelled by changing the resonance frequency of the resonator.

Abstract: The robotic cleaner includes a cleaner body that is movable and a suction unit that is movable relative to the cleaner body in a vertical direction. The suction unit includes an inlet for sucking impurities from the surface to be cleaned, and at least one support unit for spacing the inlet and the surface to be cleaned. With the configuration, the foreign substance suction efficiency from the surface to be cleaned may be improved, and a constant gap between the suction portion and the surface to be cleaned may be maintained.

Abstract: An operating method of an electronic device including a semiconductor memory, the operating method includes selecting one of a plurality of memory cells during a set operation, applying a write current having a slow quenching pattern to the selected memory cell, monitoring a cell current flowing through the selected memory cell, generating a discharge control signal corresponding to a result of the monitoring, and discharging the write current in response to the discharge control signal.

Abstract: A cleaning system is provided. The cleaning system includes a robot cleaner and a station. The robot cleaner includes a pad fixing part on which a cleaning pad is detachably mounted, a lifter to lift a part of the robot cleaner at which the pad fixing part is positioned, and a pad detacher to detach the cleaning pad mounted on the pad fixing part. The station includes a pad storage box in which a cleaning pad that is to be provided to the robot cleaner is stored, a pad coupling part on which a cleaning pad that is to be coupled to the robot cleaner is rested, and a pad supplier to supply the cleaning pad stored in the pad storage box to the pad coupling part.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes: a write circuit configured to supply a write pulse to at least one of a plurality of memory cells in a write mode, the write pulse corresponding to write data; and a write pulse conversion circuit configured to change a waveform of the write pulse, the waveform having a falling edge, the write pulse conversion circuit changing the falling edge of the wave form to have two or more slopes.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit suitable for generating a first write current at a first point of time corresponding to pre-write latency that is shorter than write latency and generating a second write current at a second point of time corresponding to the write latency, based on a write command signal, a write data signal, and a latency information signal, and a memory cell array suitable for storing a data value corresponding to the write data signal based on the first and second write currents.

Abstract: A robot cleaner including: a main body, a driving unit configured to move the main body, and a suction device provided in the main body and configured to suction outside foreign substances, and the suction device may include a first suction member having a suction port provided at a bottom surface of the main body and configured to suction the foreign substances, and at least one second suction member formed to move relative to the first suction member and having a suction port configured to suction the foreign substances.

Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a memory cell; a first line coupled to a first end of the memory cell; a first coupling circuit to selectively couple a high voltage terminal to the first line in response to a first selection signal; a second line coupled to a second end of the memory cell; a second coupling circuit to selectively couple a first low voltage terminal to the second line in response to a second selection signal; and a first charge storing circuit selectively coupled to the first line in response to an enable signal, the enable signal corresponding to a predetermined operation mode when the memory cell is turned on.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory may include: a memory circuit comprising a plurality of memory cells; a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory may include: a memory circuit comprising a plurality of memory cells; a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal.

Abstract: A method for reading data of a memory cell including a resistive memory element having a low resistance state and a high resistance state according to stored data and a selection element may include applying a recovery voltage to both ends of the memory cell, and applying a read voltage to both ends of the memory cell and sensing the data. The recovery voltage may be equal to or more than a second voltage obtained by adding a drift value of the memory cell to a first voltage for turning on the memory cell in a case in which the resistive memory element is in the low resistance state.

Abstract: By improving a structure of a discharge flow path of a robot cleaner, it may be possible to minimize a loss of a suction force, thereby reducing a noise without deteriorating cleaning efficiency. The robot cleaner includes a fan motor configured to generate a suction force, a first housing in which the fan motor is accommodated, a second housing in which the first housing is accommodated, and a chamber positioned between the first housing and the second housing, wherein a plurality of slits are formed in the chamber.

Abstract: A method for reading a data of a memory cell comprising a selection device and a resistive memory device which has a high resistance state or a low resistance state according to a data stored therein includes: applying a first read voltage to the memory cell; applying a second read voltage to the memory cell, the second read voltage having a level lower than a level of the first read voltage; and sensing the data of the memory cell while the second read voltage is applied to the memory cell.