Abstract: There is provided a semiconductor package and method for fabricating the same.

Abstract: A surface excited device package and method for packaging a surface excited device provide a surface excited device having a small footprint, high reliability, low cost and high production volume. The surface excited device may be a Surface Acoustic Wave (SAW) device or a Micro Electromechanical System(MEMS) device. A substrate including multiple conductive patterns is bonded to a semiconductor die that includes a surface excited device area. The substrate includes multiple conductive patterns for connecting electrical connections of the die and terminals for connecting the surface excited device to external devices. The substrate further includes an aperture over the surface exited device area and a cover for covering the cavity formed by the aperture to protect the surface excited device area from the external environment.

Abstract: There is provided a semiconductor package and method for fabricating the same.

Abstract: There is provided a semiconductor package and method for fabricating the same.

Abstract: There is provided a semiconductor package and method for fabricating the same.

Abstract: A semiconductor package has a substrate of an approximate planar plate comprising of an insulative layer having a plurality of land holes formed in the vicinity of an inner circumference thereof and a plurality of electrically conductive patterns formed at a surface of the insulative layer, the electrically conductive patterns comprising a plurality of bond fingers formed in the vicinity of a central portion of the insulative layer and a plurality of lands for covering the land holes connected to the bond fingers. A semiconductor die is located at a central portion of the substrate. The semiconductor die has a plurality of bond pads formed at one surface thereof. A plurality of conductive bumps is used for coupling the bond pads of the semiconductor die to the bond fingers among the electrically conductive patterns of the substrate.

Abstract: A circuit board for semiconductor package is designed to provide a complete grounding with corresponding equipment in the manufacture of the semiconductor package based on a circuit board, thereby preventing a breakdown of the circuit board or semiconductor chip caused by electrostatic charges.

Abstract: A semiconductor package including passive elements and a method of manufacturing provide reduced package size, improved performance and higher process yield by mounting the passive elements beneath the semiconductor die on the substrate. The semiconductor die may be mounted above the passive elements by mechanically bonding the semiconductor die to the passive elements, mounting the passive elements within a recess in the substrate or mounting the semiconductor using an adhesive retaining wall on the substrate that protrudes above and extends around the passive elements. The recess may include an aperture through the substrate to vent the package to the outside environment or may comprise an aperture through the substrate and larger than the semiconductor die, permitting the encapsulation to entirely fill the aperture, covering the die and the passive elements to secure them mechanically within the package.

Abstract: A thin, stackable semiconductor package having improved electrical and heat dissipating performance comprises a semiconductor chip having an integrated circuit and a plurality of input/output pads on a surface thereof. A lead frame having a plurality of inner leads with upper and a lower surfaces has one of those surfaces bonded to a surface of the chip with a bonding agent. The leads each has a projection formed on at least one of the upper and lower surfaces at a distal end portion of the lead. Each of the leads is electrically connected to an associated input/output pad of the chip through a wire bonding process using electrically conductive wires, or by a ball bonding process using electrically conductive balls. Alternatively, the leads may be directly bonded to the input/output pads of the chip by a TAB bonding process. An encapsulated portion envelops the semiconductor chip and the leads while exposing the projections of the leads to the atmosphere outside the encapsulated portion.

Abstract: A semiconductor package having a light, thin, simple and compact structure including outer leads having a minimum length and a resin encapsulate having a minimum volume. The semiconductor package includes a package body, a semiconductor chip mounted on a central portion of the body, inner and outer leads bonded to a peripheral portion of an upper surface of the body by an insulating layer in such a manner that the leads are supported on the body, conductive wires or bumps for electrically connecting the inner leads to the semiconductor chip, a resin encapsulate for encapsulating the semiconductor chip, the conductive wires or bumps and the inner leads. Each outer lead has an end positioned at a level higher than an upper surface of the semiconductor chip so that a boundary portion defined between the associated outer and inner leads serves as a barrier for the resin encapsulate. The end of each outer lead is exposed outside the resin encapsulate and extending to a peripheral edge of the body.