Abstract: A semiconductor package including a first master-slave status circuit configured to store one of a first signal or a second signal independently from a second master-slave status circuit, store the first signal in response to receiving a first initial signal from a first initialization circuit, the second master-slave status circuit configured to store one of the first signal or the second signal, store the first signal in response to receiving a second initial signal from a second initialization circuit, the first initialization circuit configured to provide the first initial signal to the first master-slave status circuit, the second initialization circuit configured to provide the second initial signal to the second master-slave status circuit, and a first master-slave determination circuit connected to the second master-slave status circuit, the first master-slave determination circuit configured to provide the second signal to the second master-slave status circuit may be provided.

Abstract: A semiconductor package including a first master-slave status circuit configured to store one of a first signal or a second signal independently from a second master-slave status circuit, store the first signal in response to receiving a first initial signal from a first initialization circuit, the second master-slave status circuit configured to store one of the first signal or the second signal, store the first signal in response to receiving a second initial signal from a second initialization circuit, the first initialization circuit configured to provide the first initial signal to the first master-slave status circuit, the second initialization circuit configured to provide the second initial signal to the second master-slave status circuit, and a first master-slave determination circuit connected to the second master-slave status circuit, the first master-slave determination circuit configured to provide the second signal to the second master-slave status circuit may be provided.

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

Abstract: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.

Abstract: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.

Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.

Abstract: A time-domain voltage comparator for an analog-to-digital converter includes a first voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; a second voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; and a phase comparator configured to determine a difference between times outputted from the first voltage-to-time converter and the second voltage-to-time converter.

Abstract: A time-to-digital converter includes a phase-difference enhancement section configured to receive first and second input signals having a reference phase difference ?t, and to output first and second output signals having an enhanced phase difference; and a comparison section configured to receive the first and second output signals, to compare a phase difference between the first and second output signals with a reference delay time ?, and to output a comparison signal. The time-to-digital converter has a high resolution. That is to say, the time-to-digital converter has a resolution less than the minimum phase delay time of a delay element, which is obtainable in a corresponding semiconductor process.

Abstract: A time-domain voltage comparator for an analog-to-digital converter includes a first voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; a second voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; and a phase comparator configured to determine a difference between times outputted from the first voltage-to-time converter and the second voltage-to-time converter.

Abstract: Provided is a microstrip transmission line for reducing far-end crosstalk. In a conventional microstrip transmission line on a printed circuit board, a capacitive coupling between adjacent signal lines is smaller than an inductive coupling therebetween, so that far-end crosstalk occurs. According to the present invention, the capacitive coupling between the adjacent signal lines is increased to reduce the far-end crosstalk. A vertical-stub type microstrip transmission line is provided.