Patents by Inventor Seon Yong Cha
Seon Yong Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145171Abstract: A capacitor component includes a body including a dielectric layer and first and second internal electrode layers, and external electrodes disposed on the body and connected to the first and second internal electrode layers, respectively. The body includes an active portion in which the first and second internal electrode layers are alternately disposed with the dielectric layer interposed therebetween, a cover portion disposed on an upper portion and a lower portion of the active portion, and a side margin portion disposed on both sides of the active portion opposing each other. When a content of magnesium (Mg) included in the active portion is A1, a content of magnesium (Mg) included in the cover portion is C1, and a content of magnesium (Mg) included in the margin portion is M1, 0<A1<M1?C1 and A1/C1?0.60 are satisfied.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Uk Cha, Chang Min Lee, Hye Sung Yoon, Seon A Jang, Ji Hyuk Lim, Ki Yong Lee
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Publication number: 20240119994Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: Seung-Hwan KIM, Su-Ock CHUNG, Seon-Yong CHA
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Publication number: 20240057309Abstract: A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.Type: ApplicationFiled: October 24, 2023Publication date: February 15, 2024Inventors: Seung Hwan KIM, Dong Sun SHEEN, Su Ock CHUNG, Il Sup JIN, Seon Yong CHA
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Patent number: 11887654Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.Type: GrantFiled: May 9, 2022Date of Patent: January 30, 2024Assignee: SK hynix Inc.Inventors: Seung-Hwan Kim, Su-Ock Chung, Seon-Yong Cha
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Patent number: 11832434Abstract: A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.Type: GrantFiled: June 24, 2021Date of Patent: November 28, 2023Assignee: SK hynix Inc.Inventors: Seung Hwan Kim, Dong Sun Sheen, Su Ock Chung, Il Sup Jin, Seon Yong Cha
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Publication number: 20230045324Abstract: A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Inventors: Seung-Hwan KIM, Su-Ock CHUNG, Seon-Yong CHA
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Patent number: 11501827Abstract: A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.Type: GrantFiled: December 27, 2019Date of Patent: November 15, 2022Assignee: SK hynix Inc.Inventors: Seung-Hwan Kim, Su-Ock Chung, Seon-Yong Cha
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Publication number: 20220262425Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.Type: ApplicationFiled: May 9, 2022Publication date: August 18, 2022Inventors: Seung-Hwan KIM, Su-Ock CHUNG, Seon-Yong CHA
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Publication number: 20220208766Abstract: A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.Type: ApplicationFiled: June 24, 2021Publication date: June 30, 2022Inventors: Seung Hwan KIM, Dong Sun SHEEN, Su Ock CHUNG, Il Sup JIN, Seon Yong CHA
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Patent number: 11355177Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.Type: GrantFiled: April 21, 2020Date of Patent: June 7, 2022Assignee: SK hynix Inc.Inventors: Seung-Hwan Kim, Su-Ock Chung, Seon-Yong Cha
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Publication number: 20210012828Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.Type: ApplicationFiled: April 21, 2020Publication date: January 14, 2021Inventors: Seung-Hwan KIM, Su-Ock CHUNG, Seon-Yong CHA
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Publication number: 20200279601Abstract: A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.Type: ApplicationFiled: December 27, 2019Publication date: September 3, 2020Inventors: Seung-Hwan KIM, Su-Ock CHUNG, Seon-Yong CHA
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Patent number: 8198161Abstract: A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions.Type: GrantFiled: October 3, 2011Date of Patent: June 12, 2012Assignee: Hynix Semiconductor Inc.Inventor: Seon Yong Cha
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Publication number: 20120021576Abstract: A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions.Type: ApplicationFiled: October 3, 2011Publication date: January 26, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Seon Yong CHA
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Patent number: 8053817Abstract: A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions.Type: GrantFiled: December 11, 2007Date of Patent: November 8, 2011Assignee: Hynix Semiconductor Inc.Inventor: Seon Yong Cha
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Patent number: 7799641Abstract: A method for forming a semiconductor device having recess channel includes forming a hard mask film pattern for exposing first regions for forming the trenches on a semiconductor substrate; forming first trenches by a first etching process using the hard mask film pattern as a mask, and removing the hard mask film pattern; forming a barrier film on the semiconductor substrate including the first trenches; forming an ion implantation mask film for exposing the first trenches on the barrier film; forming an ion implantation region in the semiconductor substrate below the first trenches using the ion implantation mask film and the barrier film; forming bulb-shaped second trenches by a second etching process using the ion implantation mask film and the barrier film as a mask, so that bulb-type trenches for recess channels, each including the first trench and the second trench, are formed; and removing the ion implantation mask film and the barrier film.Type: GrantFiled: October 11, 2006Date of Patent: September 21, 2010Assignee: Hynix Semiconductor Inc.Inventors: Jin Yul Lee, Min Ho Ha, Seon Yong Cha
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Publication number: 20100203696Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device suitable for preventing a threshold voltage of a recess gate from decreasing due to a voltage of an adjacent storage node comprises a semiconductor substrate having an active region which includes a gate area and a storage node contact area and is recess in the gate area; a device isolation structure formed in the semiconductor substrate to define the active region and having a shield layer therein; a recess gate formed in the gate area of the semiconductor substrate; and a storage node formed to be connected with the storage node contact area of the active region.Type: ApplicationFiled: April 21, 2010Publication date: August 12, 2010Applicant: Hynix Semiconductor Inc.Inventor: Seon Yong CHA
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Publication number: 20090114978Abstract: A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions.Type: ApplicationFiled: December 11, 2007Publication date: May 7, 2009Inventor: Seon Yong CHA
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Publication number: 20080290390Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device suitable for preventing a threshold voltage of a recess gate from decreasing due to a voltage of an adjacent storage node comprises a semiconductor substrate having an active region which includes a gate area and a storage node contact area and is recess in the gate area; a device isolation structure formed in the semiconductor substrate to define the active region and having a shield layer therein; a recess gate formed in the gate area of the semiconductor substrate; and a storage node formed to be connected with the storage node contact area of the active region.Type: ApplicationFiled: September 10, 2007Publication date: November 27, 2008Applicant: Hynix Semiconductor Inc.Inventor: Seon Yong Cha
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Publication number: 20080277741Abstract: A semiconductor device includes a semiconductor substrate; a source area, a channel area and a drain area vertically stacked on the semiconductor substrate; and a gate formed in both side walls of the stacked source area, channel area and drain area under interposition of a gate insulation layer.Type: ApplicationFiled: June 20, 2007Publication date: November 13, 2008Applicant: Hynix Semiconductor, Inc.Inventor: Seon Yong CHA