Abstract: A method for forming a semiconductor device having recess channel includes forming a hard mask film pattern for exposing first regions for forming the trenches on a semiconductor substrate; forming first trenches by a first etching process using the hard mask film pattern as a mask, and removing the hard mask film pattern; forming a barrier film on the semiconductor substrate including the first trenches; forming an ion implantation mask film for exposing the first trenches on the barrier film; forming an ion implantation region in the semiconductor substrate below the first trenches using the ion implantation mask film and the barrier film; forming bulb-shaped second trenches by a second etching process using the ion implantation mask film and the barrier film as a mask, so that bulb-type trenches for recess channels, each including the first trench and the second trench, are formed; and removing the ion implantation mask film and the barrier film.

Abstract: The present invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof. The whole cells are connected to each other by using a substrate as a ground terminal and a vertical structure field effect transistor (FET) for connecting the cells to the bit line. Thus, the MRAM is easily manufactured without requiring a special process for isolation of each cell. The MRAM uses the vertical structure FET to simplify the whole manufacturing process. An MTJ cell mask process which is essential in a general horizontal structure FET is omitted, to improve a speed of the MRAM and attain high integration of the MRAM.

Abstract: The present invention discloses an MRAM wherein a write word line is disposed between every other set of the word lines and a ground line is disposed between every other bit lines. This structure of MRAM in accordance with the present invention, Which is similar to folded bit line DRAM having a unit cell area of 8F2, allows read and write operation of MRAM with reduced number of required lines.

Abstract: The present invention generally relates to a NAND-type magnetoresistive RAM, and more specifically, to a NAND-type magnetoresistive RAM comprising a plurality of transistors connected in series as a NAND-type which can reduce the effective area per cell. Two or more NAND-type transistors sharing an adjacent source region and an adjacent drain region are connected in series, thereby reducing inactive regions. A read node connected to a bitline is shared by a plurality of transistors, thereby improving a read operation. As a result, the effective area per cell can be decreased, and the integration of a device can be improved.

Abstract: A magnetic random access memory (MRAM) having a vertical structure transistor has the characteristics of faster access time than SRAM, high density as with DRAM, and non-volatility like a flash memory device. The MRAM has a vertical structure transistor, a first word line including the transistor, a contact line connected to the transistor, a magnetic tunnel junction (MTJ) cell deposited on the contact line, a bit line deposited on the MTJ cell, and a second word line deposited on the bit line at the position of MTJ cell. With the disclosed structure, it is possible to improve the integration density of a semiconductor device, to increase the short channel effect, and to improve the control rate of the resistance, while using a simplified manufacturing process.

Abstract: The present invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof. The whole cells are connected to each other by using a substrate as a ground terminal and a vertical structure field effect transistor (FET) for connecting the cells to the bit line. Thus, the MRAM is easily manufactured without requiring a special process for isolation of each cell. The MRAM uses the vertical structure FET to simplify the whole manufacturing process. An MTJ cell mask process which is essential in a general horizontal structure FET is omitted, to improve a speed of the MRAM and attain high integration of the MRAM.

Abstract: The present invention generally relates to a NAND-type magnetoresistive RAM, and more specifically, to a NAND-type magnetoresistive RAM comprising a plurality of transistors connected in series as a NAND-type which can reduce the effective area per cell. Two or more NAND-type transistors sharing an adjacent source region and an adjacent drain region are connected in series, thereby reducing inactive regions. A read node connected to a bitline is shared by a plurality of transistors, thereby improving a read operation. As a result, the effective area per cell can be decreased, and the integration of a device can be improved.

Abstract: A magnetic random access memory (MRAM) having a vertical structure transistor has the characteristics of faster access time than SRAM, high density as with DRAM, and non-volatility like a flash memory device. The MRAM has a vertical structure transistor, a first word line including the transistor, a contact line connected to the transistor, a magnetic tunnel junction (MTJ) cell deposited on the contact line, a bit line deposited on the MTJ cell, and a second word line deposited on the bit line at the position of MTJ cell. With the disclosed structure, it is possible to improve the integration density of a semiconductor device, to increase the short channel effect, and to improve the control rate of the resistance, while using a simplified manufacturing process.

Abstract: A magnetic random access memory (MRAM) having a vertical structure transistor has the characteristics of faster access time than SRAM, high density as with DRAM, and non-volatility like a flash memory device. The MRAM has a vertical structure transistor, a first word line including the transistor, a contact line connected to the transistor, a magnetic tunnel junction (MTJ) cell deposited on the contact line, a bit line deposited on the MTJ cell, and a second word line deposited on the bit line at the position of MTJ cell. With the disclosed structure, it is possible to improve the integration density of a semiconductor device, to increase the short channel effect, and to improve the control rate of the resistance, while using a simplified manufacturing process.

Abstract: The present invention discloses a method for fabricating a semiconductor device. In an open bit line cell aligned local interconnection type device having a minimum line width of 1F and a pattern interval of 1F, hard masks are formed on respective conductive layers, and insulating spacers are formed at the side walls thereof, thereby preventing the adjacent conductive layers from being shorted out and maintaining the minimum pattern interval. As a result, a high, integration of the device is achieved, and the process yield and reliability of the device are improved.

Abstract: A magnetic random access memory (MRAM) having a vertical structure transistor has the characteristics of faster access time than SRAM, high density as with DRAM, and non-volatility like a flash memory device. The MRAM includes a vertical structure transistor, a first word line including the transistor, a contact line connected to the transistor, a magnetic tunnel junction (MTJ) cell deposited on the contact line, a bit line deposited on the MTJ cell, and a second word line deposited on the bit line at the position of MTJ cell. With the disclosed structure, it is possible to improve the integration density of a semiconductor device, to increase the short channel effect, and to improve the control rate of the resistance, while using a simplified manufacturing process.

Abstract: The present invention discloses a method for fabricating a semiconductor device. In an open bit line cell aligned local interconnection type device having a minimum line width of 1F and a pattern interval of 1F, hard masks are formed on respective conductive layers, and insulating spacers are formed at the side walls thereof, thereby preventing the adjacent conductive layers from being shorted out and maintaining the minimum pattern interval. As a result, a high integration of the device is achieved, and the process yield and reliability of the device are improved.