Patents by Inventor Seong Jae Choi

Seong Jae Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12166101
    Abstract: A method of manufacturing a high-electron-mobility transistor device is provided. The method includes sequentially forming a transition layer and a semiconductor layer on a substrate, etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region, forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer, forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer, and forming a gate electrode on the upward exposed barrier layer.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: December 10, 2024
    Assignee: ELECTRONICS AND TELECOMMINICATIONS RESEARCH INSTITUTE
    Inventors: Soo Cheol Kang, Hyun Wook Jung, Seong IL Kim, Hae Cheon Kim, Youn Sub Noh, Ho Kyun Ahn, Sang Heung Lee, Jong Won Lim, Sung Jae Chang, Il Gyu Choi
  • Patent number: 12131978
    Abstract: The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: October 29, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Il Gyu Choi, Seong Il Kim, Hae Cheon Kim, Youn Sub Noh, Ho Kyun Ahn, Sang Heung Lee, Jong Won Lim, Sung Jae Chang, Hyun Wook Jung
  • Publication number: 20240341189
    Abstract: Disclosed are a polycyclic compound with a specific fused ring structure and an organic light emitting device including a light emitting layer that employs the polycyclic compound. The use of the polycyclic compound ensures significantly long lifetime and improved luminous efficiency of the device.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 10, 2024
    Inventors: Ji-hwan Kim, Kyung-Hwa Park, Hyeon-jun Jo, Seong-eun Woo, Soo-kyung Kang, Da-Yeon Lee, Hui-Jae Choi, Ji-hyun Lee, Sung-hoon Joo
  • Patent number: 12110897
    Abstract: A fan motor for a vacuum cleaner includes a motor mount defining a cooling flow path inlet, an impeller, an impeller cover defining an air inlet, an air discharge opening defined at the motor mount and configured to discharge air to an outer space of the motor mount, and a cooling flow path outlet defined vertically above the motor mount. The cooling flow path inlet is configured to introduce air from the outer space of the motor mount into an inner space of the motor mount to cool the motor part, and the cooling flow path outlet is configured to discharge air from the inner space of the motor mount toward a space that is defined between the impeller and the air discharge opening based on the space between the impeller and the air discharge opening having a lower pressure than the inner space of the motor mount.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: October 8, 2024
    Assignee: LG Electronics Inc.
    Inventors: Jeong Ho Lee, Seong-Jae Kim, Seung Jo Baek, Young Gyu Jung, Hak Kyu Choi, Seong-Ho Cho
  • Publication number: 20240299970
    Abstract: A slot die coater that includes a lower die block having a manifold, an upper die block, and a shim plate interposed between the lower die block and the upper die block to form a slot. The manifold configured to accommodate a coating solution, wherein the coating solution is delivered and coated on a substrate through an exit port in communication with the slot. The shim plate includes a plate-shaped member having an open portion which is cut in at least an area to determine a coating width of a coating layer coated on the substrate, and a structure protruding from the plate-shaped member and inserted into the manifold.
    Type: Application
    Filed: November 4, 2022
    Publication date: September 12, 2024
    Applicant: LG Energy Solution, Ltd.
    Inventors: Young-Joon Jo, Seong-Jae You, Taek-Soo Lee, Min-Hyuck Choi, Shin-Wook Jeon, Sang-Hoon Choy
  • Patent number: 12062365
    Abstract: An apparatus for training a dialogue summary model according to an embodiment includes a parameter transferer configured to transfer one or more learning parameter values of a pre-trained natural language processing model to a sequence-to-sequence-based dialogue summary model, and a model trainer configured to train the dialogue summary model by using the transferred learning parameter values as initial values for learning parameters of each of an encoder and a decoder in the dialogue summary model.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: August 13, 2024
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Hyun Jae Lee, Hyun Jin Choi, Jae Woong Yun, Ju Dong Kim, Bong Kyu Hwang, Seong Ho Joe, Young June Gwon
  • Publication number: 20240266251
    Abstract: A direct cooling type semiconductor package unit includes a substrate made of a material capable of manufacturing a semiconductor device, and having a material layer for forming the semiconductor device stacked on one side of the substrate, and a flow channel through which a cooling fluid flows formed on the other side of the substrate to enable direct cooling of the semiconductor device using the cooling fluid; a packaging block disposed at a position spaced apart from the substrate for packaging the semiconductor device, and having an electrode electrically connected to the semiconductor device through wiring and placed thereon to be insulated; a heat sink unit disposed on a lower side of the packaging block and having a fluid movement region formed at a position corresponding to a flow channel of the substrate; and a thin film type structure disposed between the substrate and the heat sink unit for coupling between the substrate and the heat sink unit and being moldable to have pattern structures of variou
    Type: Application
    Filed: February 4, 2024
    Publication date: August 8, 2024
    Inventors: Jun Rae PARK, Min Soo KANG, Hae Cheon KIM, Hyoung Soon LEE, Sung Jae CHANG, Hyun Wook JUNG, Il Gyu CHOI, Seong Il KIM, Sang Heung LEE, Ho Kyun AHN, Jong Won LIM
  • Publication number: 20240266253
    Abstract: Provided is a direct cooling device for an integrated circuit configured to form a direct cooling portion with a flow channel through which cooling fluid may flow in a through via hole of a substrate constituting the integrated circuit, and to couple the substrate to a heat sink unit through a bonding portion formed integrally with the direct cooling portion, unlike the prior art in which only a ground circuit is possible through the through via hole, which derives the effect of increasing product reliability due to improved thermal management efficiency of the integrated circuit by directly cooling the semiconductor device as well as the ground circuit, and the effect of simplifying and miniaturizing the structure by implementing the cooling function using a circuit for grounding the semiconductor device even without forming an additional flow path structure for cooling the semiconductor device.
    Type: Application
    Filed: February 4, 2024
    Publication date: August 8, 2024
    Inventors: Min Soo KANG, Jun Rae PARK, Hae Cheon KIM, Hyoung Soon LEE, Sung Jae CHANG, Hyun Wook JUNG, Il Gyu CHOI, Seong Il KIM, Sang Heung LEE, Ho Kyun AHN, Jong Won LIM
  • Publication number: 20240253178
    Abstract: A composite polishing pad for chemical mechanical polishing (CMP) and a method for producing the composite CMP. The composite polishing pad for CMP contains a polymer substrate layer including a plurality of protrusions formed on the upper surface thereof; and a carbon nanotube layer including carbon nanotubes embedded in and fixed to the upper portion of the substrate layer.
    Type: Application
    Filed: November 12, 2021
    Publication date: August 1, 2024
    Applicants: KPX CHEMICAL CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Byung Ju MIN, Seok Ji HONG, Seung Geun KIM, Jung Hee CHOI, Min Woo KANG, Nam Gue OH, Sanha KIM, Ji Hun JEONG, Hyun Jun RYU, Sukkyung KANG, Seong Jae KIM
  • Patent number: 10920134
    Abstract: Disclosed herein is a method for preparing a multilayer of nanocrystals. The method comprises the steps of (i) coating nanocrystals surface-coordinated by a photosensitive compound, or a mixed solution of a photosensitive compound and nanocrystals surface-coordinated by a material miscible with the photosensitive compound, on a substrate, drying the coated substrate, and exposing the dried substrate to UV light to form a first monolayer of nanocrystals, and (ii) repeating the procedure of step (i) to form one or more monolayers of nanocrystals on the first monolayer of nanocrystals.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Joo Jang, Shin Ae Jun, Sung Hun Lee, Jong Jin Park, Seong Jae Choi, Tae Kyung Ahn
  • Patent number: 10202545
    Abstract: Disclosed herein is a nanocrystal comprising a core comprising a first nanocrystal material, the first nanocrystal material including a Group II-VI semiconductor compound or a Group III-V semiconductor compound; a shell being disposed upon a surface of the core and comprising a second nanocrystal material, the second nanocrystal material being different from the first nanocrystal material and including a Group II-VI semiconductor compound or a Group III-V semiconductor compound; and an alloy interlayer disposed between the core and the shell, wherein the emission peak wavelength of the nanocrystal is shifted into a shorter wavelength than the emission peak wavelength of the core.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shin Ae Jun, Eun Joo Jang, Seong Jae Choi
  • Patent number: 9902902
    Abstract: Disclosed herein is a quantum dot phosphor for light emitting diodes, which includes quantum dots and a solid substrate on which the quantum dots are supported. Also, a method of preparing the quantum dot phosphor is provided. Since the quantum dot phosphor of the current invention is composed of the quantum dots supported on the solid substrate, the quantum dots do not aggregate when dispensing a paste obtained by mixing the quantum dots with a paste resin for use in packaging of a light emitting diode. Thereby, a light emitting diode able to maintain excellent light emitting efficiency can be manufactured.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Joo Jang, Mi Yang Kim, Hyung Kun Kim, Shin Ae Jun, Yong Wan Jin, Seong Jae Choi
  • Publication number: 20170237029
    Abstract: Disclosed herein is a nanocrystal comprising a core comprising a first nanocrystal material, the first nanocrystal material including a Group II-VI semiconductor compound or a Group III-V semiconductor compound; a shell being disposed upon a surface of the core and comprising a second nanocrystal material, the second nanocrystal material being different from the first nanocrystal material and including a Group II-VI semiconductor compound or a Group III-V semiconductor compound; and an alloy interlayer disposed between the core and the shell, wherein the emission peak wavelength of the nanocrystal is shifted into a shorter wavelength than the emission peak wavelength of the core.
    Type: Application
    Filed: April 28, 2017
    Publication date: August 17, 2017
    Inventors: Shin Ae JUN, Eun Joo JANG, Seong Jae CHOI
  • Publication number: 20170190966
    Abstract: Disclosed herein is a method for preparing a multilayer of nanocrystals. The method comprises the steps of (i) coating nanocrystals surface-coordinated by a photosensitive compound, or a mixed solution of a photosensitive compound and nanocrystals surface-coordinated by a material miscible with the photosensitive compound, on a substrate, drying the coated substrate, and exposing the dried substrate to UV light to form a first monolayer of nanocrystals, and (ii) repeating the procedure of step (i) to form one or more monolayers of nanocrystals on the first monolayer of nanocrystals.
    Type: Application
    Filed: March 20, 2017
    Publication date: July 6, 2017
    Inventors: Eun Joo JANG, Shin Ae JUN, Sung Hun LEE, Jong Jin PARK, Seong Jae CHOI, Tae Kyung AHN
  • Patent number: 9637682
    Abstract: Disclosed herein is a nanocrystal comprising a core comprising a first nanocrystal material, the first nanocrystal material including a Group II-VI semiconductor compound or a Group III-V semiconductor compound; a shell being disposed upon a surface of the core and comprising a second nanocrystal material, the second nanocrystal material being different from the first nanocrystal material and including a Group II-VI semiconductor compound or a Group III-V semiconductor compound; and an alloy interlayer disposed between the core and the shell, wherein the emission peak wavelength of the nanocrystal is shifted into a shorter wavelength than the emission peak wavelength of the core.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: May 2, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shin Ae Jun, Eun Joo Jang, Seong Jae Choi
  • Patent number: 9598634
    Abstract: Disclosed herein is a method for preparing a multilayer of nanocrystals. The method comprises the steps of (i) coating nanocrystals surface-coordinated by a photosensitive compound, or a mixed solution of a photosensitive compound and nanocrystals surface-coordinated by a material miscible with the photosensitive compound, on a substrate, drying the coated substrate, and exposing the dried substrate to UV light to form a first monolayer of nanocrystals, and (ii) repeating the procedure of step (i) to form one or more monolayers of nanocrystals on the first monolayer of nanocrystals.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: March 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Joo Jang, Shin Ae Jun, Sung Hun Lee, Jong Jin Park, Seong Jae Choi, Tae Kyung Ahn
  • Publication number: 20170037309
    Abstract: Disclosed herein is a quantum dot phosphor for light emitting diodes, which includes quantum dots and a solid substrate on which the quantum dots are supported. Also, a method of preparing the quantum dot phosphor is provided. Since the quantum dot phosphor of the current invention is composed of the quantum dots supported on the solid substrate, the quantum dots do not aggregate when dispensing a paste obtained by mixing the quantum dots with a paste resin for use in packaging of a light emitting diode. Thereby, a light emitting diode able to maintain excellent light emitting efficiency can be manufactured.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Inventors: Eun Joo JANG, Mi Yang KIM, Hyung Kun KIM, Shin Ae JUN, Yong Wan JIN, Seong Jae CHOI
  • Patent number: 9475984
    Abstract: Disclosed herein is a quantum dot phosphor for light emitting diodes, which includes quantum dots and a solid substrate on which the quantum dots are supported. Also, a method of preparing the quantum dot phosphor is provided. Since the quantum dot phosphor of the current invention is composed of the quantum dots supported on the solid substrate, the quantum dots do not aggregate when dispensing a paste obtained by mixing the quantum dots with a paste resin for use in packaging of a light emitting diode. Thereby, a light emitting diode able to maintain excellent light emitting efficiency can be manufactured.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: October 25, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Joo Jang, Mi Yang Kim, Hyung Kun Kim, Shin Ae Jun, Yong Wan Jin, Seong Jae Choi
  • Patent number: 9117945
    Abstract: Disclosed are a carbon nano-tube (CNT) thin film treated with chemical having an electron withdrawing functional group and a manufacturing method thereof. Specifically, the CNT thin film comprises a CNT composition to be applied on a plastic substrate. The CNT composition comprises a CNT; and chemical connected to the CNT and having an electron withdrawing functional group. In addition, the method for manufacturing a CNT thin film comprises steps of preparing a CNT; treating the CNT with chemical having an electron withdrawing functional group; mixing the CNT treated with the chemical with a dispersing agent or dispersing solvent to prepare a CNT dispersed solution; and forming a CNT thin film with the CNT dispersed solution. According to the CNT thin film and the manufacturing method thereof, a resistance of an electrode is decreased to improve the electric conductivity of the electrode.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: August 25, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeon Jin Shin, Seonmi Yoon, Jaeyoung Choi, Young Hee Lee, Seong Jae Choi, Soo Min Kim
  • Patent number: 9090817
    Abstract: Disclosed herein is a quantum dot phosphor for light emitting diodes, which includes quantum dots and a solid substrate on which the quantum dots are supported. Also, a method of preparing the quantum dot phosphor is provided. Since the quantum dot phosphor of the current invention is composed of the quantum dots supported on the solid substrate, the quantum dots do not aggregate when dispensing a paste obtained by mixing the quantum dots with a paste resin for use in packaging of a light emitting diode. Thereby, a light emitting diode able to maintain excellent light emitting efficiency can be manufactured.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: July 28, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Joo Jang, Mi Yang Kim, Hyung Kun Kim, Shin Ae Jun, Yong Wan Jin, Seong Jae Choi