Abstract: The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface.

Abstract: The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface.

Abstract: A method for assigning a channel in multi-FA CDMA mobile communication system according to the received power prevents communication quality of a FA from being inferior to that of the others by managing the interference level of the FA. The method. comprises the steps of: comparing a first threshold value with received power when the base station receives a new call request; assigning a traffic channel in a first FA of the request, if the received power is less than the first threshold value, and searching a second FA of which received power is least, if not; comparing a second threshold value with the received power of the second FA; and assigning a traffic channel in the second FA if the received power is less than the second threshold value, and rejecting the request, if not.

Abstract: A method of fabricating a MOS transistor having shallow source/drain junction regions is provided. A diffusion source layer is formed on a semiconductor substrate on which gate patterns are formed. Same type or different type of impurities are implanted into the diffusion source layer several times in different directions. As a result, dislocation does not occur and the impurity concentration of the diffusion source layer can be nonuniformly controlled so that damage to the crystal structure of the semiconductor substrate does not occur. Also, the impurities nonuniformly contained in the diffusion source layer are diffused into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD regions and highly doped source/drain regions by a self-alignment method.

Abstract: The present invention relates to a method of manufacturing a nano transistor. The present invention manufactures the nano transistor without changing a conventional method of forming the nano transistor formed on a SOI substrate. Further, the present invention includes forming a N well and a P well at given regions of an underlying silicon substrate so that a given voltage can be individually applied to a NMOS transistor and a PMOS transistor. Therefore, the present invention can control the threshold voltage to prevent an increase of the leakage current.

Abstract: A method of fabricating a MOS transistor having shallow source/drain junction regions is provided. A diffusion source layer is formed on a semiconductor substrate on which gate patterns are formed. Same type or different type of impurities are implanted into the diffusion source layer several times in different directions. As a result, dislocation does not occur and the impurity concentration of the diffusion source layer can be nonuniformly controlled so that damage to the crystal structure of the semiconductor substrate does not occur. Also, the impurities nonuniformly contained in the diffusion source layer are diffused into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD regions and highly doped source/drain regions by a self-alignment method.

Abstract: A method of fabricating an integrated circuit having shallow junctions is provided. A SOG layer containing impurities is formed on a semiconductor substrate. Impurity ions are additionally implanted into the SOG layer by a plasma ion implantation method to increase the concentration of impurities in the SOG layer. The impurity ions contained in the SOG layer having the increased concentration of impurities are rapidly heat-treated and diffused into the semiconductor substrate by a solid phase diffusion method to form shallow junctions. As a result, the concentration of impurities is precisely controlled by the plasma ion implantation method, and impurity ions are not directly implanted into the semiconductor substrate. Thus, the crystal structure of the semiconductor substrate is not damaged.

Abstract: The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface.

Abstract: A single-electron memory device using the electron-hole Coulomb blockade is provided. A single-electron memory device in accordance with an embodiment of the present invention includes a plurality of quantum dot tunnel-junction arrays, a gate electrode, and source and drain electrodes. The plurality of quantum dot tunnel-junction arrays include at least two tunnel-junctions, are parallelly coupled to each other, and are well separated from each other to prevent single-electron tunneling between them. One of the plurality of quantum dot tunnel-junction arrays includes the gate electrode, and the voltage applied to the gate electrode can vary the number of electron-hole pairs.

Abstract: The present invention is to fabricate SOI wafer whose the silicon layer is very uniform and the impurity concentration is low. The insulating layer, that is, a composite layer of SiO2 and silicon, is grown on oxide substrate by means of a molecular beam epitaxy fabricating method using silicon as an original material in the oxygen atmosphere. The composite layer of the oxide and silicon is grown according to gradual decreasing the pressure of oxygen atmosphere. A top silicon layer of uniform thickness is grown by means of a molecular beam epitaxy fabricating method using only silicon material consecutively on the composite layer.

Abstract: The present invention discloses a technique for applying diffraction characteristic of electrons to a two-dimensional electronic device to manufacture multi-functional transistor having various ON/OFF states. A quantum diffraction transistor according to the present invention is capable of adjusting the amplitude of drain current and having various ON/OFF states utilizing diffraction characteristic of electrons by interposing a reflection-type diffraction grating in an electron path. The inventive multi-functional quantum diffraction transistor uses a two dimensional electron gas in formed at a different species junction in a semiconductor heterostructure, and has a bent electron path between the source electrode and the drain electrode with a reflection-type diffraction grating. The quantum diffraction effect of the electrons is used for the control of the diffracted drain current.

Abstract: The present invention discloses a technique for applying diffraction characteristics of electrons to a two-dimensional electronic device to manufacture multi-functional transistor having various ON/OFF states. Method of manufacturing a quantum diffraction transistor according to the present invention is capable of adjusting the amplitude of drain current and having various ON/OFF states utilizing diffraction characteristics of electrons by interposing a reflection-type diffraction grating in a bent electron path. In the inventive multi-functional quantum diffraction transistor using a two dimensional electron gas in quantum well structure formed at a different species junction in a heterostructure semiconductor device and having a bent electron path between the source electrode and the drain electrode with a reflection-type diffraction grating, the quantum diffraction effect of the electrons is used for the control of the diffracted drain current.

Abstract: A transistor in accordance with the invention comprises an ultra-thin Mo--C film functioning as a channel for an electron flow with two ends of the thin metal film functioning as source and drain terminals of the transistor, respectively; a piezoelectric film formed on the Mo--C film, for producing a force in accordance with an applied electric field provided by a gate voltage; and an electrode film formed on the piezoelectric film functioning as a gate of the transistor to which the gate voltage is applied to produce the applied electric field; and wherein a resistance of the Mo--C film between the source and drain terminals changes in accordance with the force produced in response to the applied gate voltage. This transistor can be used as an element of the three dimensional integrated circuit with a laminated structure.

Abstract: A lateral resonant tunneling transistor having two non-symmetric quantum dots is disclosed. When a negative voltage is supplied to each plurality of thin split gates, two non-symmetric quantum dots are formed owing to the formation of the potential barrier. Thus when a forward bias voltage is applied, the resonant tunneling phenomena occur twice successively. Through these two successive resonant tunneling phenomena and by lowering the height of the third potential barrier 6a, the resonant tunneling current can be maximized.

Abstract: A thin film transistor is disclosed comprising a piezoelectric film formed on a piezoresistive body of an ultra thin film and a gate electrode formed on the piezoelectric film. Due to the force generated from the piezoelectric film by an electric field generated according to the strength of a voltage applied to the gate electrode, a pressure is applied on the piezoresistive body to vary the resistance of the piezoresistive body. Thus, the quantity of current that flows from a source terminal through the piezoresistive channel to a drain terminal can be controlled. Since the piezoresistive body can be formed on a plane, a thin film transistor with a three-dimensional structure can be manufactured.

Abstract: Disclosed is the method of producing a piezo-device utilizing an ultra-thin Mo-C film as a piezoresistive material for a general class of improved piezo-device with the high sensitivity and the weak temperature dependence.

Abstract: A quantum interference device comprises a semi-insulating GaAs substrate; GaAs and AlGaAs layers sequentially formed with high purity on the substrate; a two-dimensional electron gas layer formed in the GaAs layer and serving as a channel; source/drain regions formed on the semi-insulating GaAs substrate and at both ends of a laminated portion composed of the GaAs/AlGaAs layers; and a gate formed on the AlGaAs layer and having a periodic structure wherein the length thereof varies in a periodic manner in a transverse direction. In the device, the electron gas layer formed in the GaAs layer is used as an electron path, and the phases of electrons passing along different electron paths are caused to interfere with each other by the gate, thereby causing the current of a drain therein to be maximized or minimized. The transconductance can be significantly increased.