Patents by Inventor Seong-Jun Heo
Seong-Jun Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240123548Abstract: Embodiments relate to laser welding methods, monitoring methods, and monitoring systems for a secondary battery. A laser welding method for a secondary battery includes performing laser welding on a positive electrode base having a thin-film shape in which a plurality of positive electrode base tabs are formed at a side, a negative electrode base having a thin-film shape in which a plurality of negative electrode base tabs are formed at a side, and a thin-film multi-tab to be joined to each of the positive electrode base and the negative electrode base, a welded portion in which the multi-tab is welded with the positive electrode base and the negative electrode base being melting-joined by using a laser such that a plurality of welding spots is formed on the welded portion.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Inventors: Jae Hoon ROH, Sang Hyun RYU, Myung Jun PARK, Seong Bae AN, Yong Gyu AN, Hee Dong JUNG, Jin Gyu HEO
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Patent number: 11453262Abstract: A void bush for a vehicle suspension includes: inside bumps formed in an inside stopper and outside bumps formed in an outside stopper. In particular, the inside bumps and the outside bumps are configured to cross perpendicularly to each other to allow the inside bumps and the outside bumps to be brought into point-contact with each other during behavior of the suspension. The inside bumps are not arranged in parallel to each other and the outside bumps are not arranged in parallel to each other. Accordingly, contact area between the inside bumps and the outside bumps is greatly reduced and contact abrasion positions therebetween are diversified so that durability and lifespan of the void bush are improved.Type: GrantFiled: November 4, 2020Date of Patent: September 27, 2022Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATIONInventors: Dae Un Sung, Kyung Jung Hwang, Yong Hyun Ryu, Hee Jung Lee, Tae Hee Lee, Se Young Kim, Jin Wook Park, Seong Jun Heo
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Publication number: 20210138859Abstract: A void bush for a vehicle suspension includes: inside bumps formed in an inside stopper and outside bumps formed in an outside stopper. In particular, the inside bumps and the outside bumps are configured to cross perpendicularly to each other to allow the inside bumps and the outside bumps to be brought into point-contact with each other during behavior of the suspension. The inside bumps are not arranged in parallel to each other and the outside bumps are not arranged in parallel to each other. Accordingly, contact area between the inside bumps and the outside bumps is greatly reduced and contact abrasion positions therebetween are diversified so that durability and lifespan of the void bush are improved.Type: ApplicationFiled: November 4, 2020Publication date: May 13, 2021Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATIONInventors: Dae Un SUNG, Kyung Jung HWANG, Yong Hyun RYU, Hee Jung LEE, Tae Hee LEE, Se Young KIM, Jin Wook PARK, Seong Jun HEO
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Patent number: 7772643Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).Type: GrantFiled: June 8, 2009Date of Patent: August 10, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Ja-Hum Ku, Chang-Won Lee, Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim
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Publication number: 20090250752Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).Type: ApplicationFiled: June 8, 2009Publication date: October 8, 2009Inventors: Ja-Hum Ku, Chang-Won Lee, Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim
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Patent number: 7544996Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).Type: GrantFiled: August 3, 2006Date of Patent: June 9, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Ja-Hum Ku, Chang-Won Lee, Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim
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Patent number: 7465617Abstract: A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.Type: GrantFiled: November 9, 2005Date of Patent: December 16, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ja-Hum Ku, Chang-Won Lee, Seong-Jun Heo, Min-Chul Sun, Sun-Pil Youn
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Patent number: 7306996Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).Type: GrantFiled: August 3, 2006Date of Patent: December 11, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Ja-Hum Ku, Chang-Won Lee, Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim
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Publication number: 20060270205Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).Type: ApplicationFiled: August 3, 2006Publication date: November 30, 2006Inventors: Ja-Hum Ku, Chang-Won Lee, Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim
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Publication number: 20060270204Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).Type: ApplicationFiled: August 3, 2006Publication date: November 30, 2006Inventors: Ja-Hum Ku, Chang-Won Lee, Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim
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Patent number: 7109104Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).Type: GrantFiled: September 22, 2003Date of Patent: September 19, 2006Assignee: Samsung Electronics Ltd., Co.Inventors: Ja-Hum Ku, Chang-Won Lee, Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim
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Patent number: 7098123Abstract: Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.Type: GrantFiled: February 17, 2004Date of Patent: August 29, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim, Si-Young Choi, Gil-Heyun Choi, Ja-Hum Ku, Chang-Won Lee, Jong-Myeong Lee, Kwon-Sun Ryu
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Publication number: 20060163677Abstract: Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.Type: ApplicationFiled: March 22, 2006Publication date: July 27, 2006Inventors: Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim, Si-Young Choi, Gil-Heyun Choi, Ja-Hum Ku, Chang-Won Lee, Jong-Myeong Lee, Kwon-Sun Ryu
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Publication number: 20060057807Abstract: A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.Type: ApplicationFiled: November 9, 2005Publication date: March 16, 2006Inventors: Ja-Hum Ku, Chang-Won Lee, Seong-Jun Heo, Min-Chul Sun, Sun-Pil Youn
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Patent number: 7005367Abstract: A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.Type: GrantFiled: July 3, 2003Date of Patent: February 28, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Ja-Hum Ku, Chang-Won Lee, Seong-Jun Heo, Min-Chul Sun, Sun-Pil Youn
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Patent number: 6960515Abstract: In a method of forming a metal gate electrode, an annealing process is performed in a hydrogen-containing gas ambient following a selective oxidation process. During the annealing process, a metal oxide layer formed by the selective oxidation process is removed by a reduction reaction or hydrogen atoms are contained in the metal oxide layer to suppress whisker nucleation and surface mobility.Type: GrantFiled: December 4, 2001Date of Patent: November 1, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Mahn-Ho Cho, Ja-Hum Ku, Chul-Joon Choi, Jun-Kyu Cho, Seong-Jun Heo
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Publication number: 20050020042Abstract: Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.Type: ApplicationFiled: February 17, 2004Publication date: January 27, 2005Inventors: Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim, Si-Young Choi, Gil-Heyun Choi, Ja-Hum Ku, Chang-Won Lee, Jong-Myeong Lee, Kwon-Sun Ryu
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Publication number: 20040238876Abstract: Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming such devices. Between forming a polysilicon layer and a metal layer, an interface reaction preventing layer is created. This reaction preventing layer prevents a buildup of highly resistive materials that would otherwise occur when creating conventional semiconductor devices, as well as having other functions.Type: ApplicationFiled: May 29, 2003Publication date: December 2, 2004Inventors: Sunpil Youn, Seong-Jun Heo, Sung-Man Kim, Chang-Won Lee, Ja-Hum Ku, Siyoung Choi
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Patent number: 6797559Abstract: A method of manufacturing a semiconductor device having a metal conducting layer is provided. A metal conducting layer pattern having the metal conducting layer is formed on a semiconductor substrate. A portion of the metal conducting layer is partially exposed on the semiconductor substrate. The semiconductor substrate having the metal conducting layer pattern is loaded into a reaction chamber. A first silicon source gas is flowed into the reaction chamber. A silicon oxide layer is formed on the semiconductor substrate having the metal conducting layer pattern by supplying a second silicon source gas and an oxygen source gas into the reaction chamber.Type: GrantFiled: October 30, 2002Date of Patent: September 28, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-won Lee, Si-young Choi, Seong-jun Heo, Sung-man Kim, Min-chul Sun, Ja-hum Ku, Sun-pil Youn
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Patent number: 6764961Abstract: The present invention includes a method of forming a metal gate electrode on which whiskers are not formed after performing a selective oxidation process and a subsequent heating process. The metal gate electrode is formed by forming a metal gate electrode pattern which is comprised of a polysilicon layer and a metal layer, and performing a selective oxidation process. After the selective oxidation process, the metal gate electrode undergoes a subsequent heating treatment. The selective oxidation process is carried out in a nitrogen containing gas ambient, so that a metal oxide layer is minimally formed on the metal layer. As a result, it is prevented from causing whiskers on the metal layer.Type: GrantFiled: November 6, 2001Date of Patent: July 20, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Ja-Hum Ku, Mahn-Ho Cho, Chul-Joon Choi, Seong-Jun Heo, Jun-Kyu Cho