Abstract: An electrodeionization filter includes: a housing having a water inlet and a water outlet; a first electrode installed inside the housing in a spiral shape; a second electrode installed inside the housing in a spiral shape so as to be spaced apart from the first electrode; and an ion exchange module installed between the first electrode and the second electrode for adsorbing or desorbing ionic substances contained in water introduced by an application of electricity. At least one of the first electrode and the second electrode has a structure in which a center portion thereof is denser than a peripheral region thereof. Accordingly, the lifespan of the electrodes of the electrodeionization filter can be increased, and the assembly of the electrodes and related parts can be easily facilitated.

Abstract: A magnetic memory device includes a lower contact plug on a substrate and a data storage structure on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.

Abstract: The technology relates to an integrated circuit (IC) package in which an interconnection interface chiplet and/or interconnection interface circuit are relocated, partitioned, and/or decoupled from a main or core IC die and/or high-bandwidth memory (HBM) components in an integrated component package.

Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

Abstract: The present disclosure may be a deep learning-based method for improving feature map compression efficiency, wherein feature maps can be selectively transmitted from an encoder, and untransmitted feature maps can be predicted and generated after restoring the image quality of the transmitted feature maps using a deep neural network.

Abstract: A method for producing a lead-free X-ray shielding material using bismuth iodide is provided, the method including a first step of producing porous PDMS (Polydimethylsiloxane); a second step of producing a mixed solution of BiI3 and THF; and a third step of immersing the porous PDMS into the mixed solution such that the BiI3 is loaded into the porous PDMS to produce a BiI3-PDMS composite material.

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

Abstract: Disclosed is a method of manufacturing a transparent stretchable substrate according to various embodiments of the present disclosure. The method may include generating a substrate part formed of an elastic material, generating an auxetic including a plurality of unit structures on the substrate part, and generating a fixing part on the substrate part on which the auxetic is generated.

Abstract: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may be formed as an integral part of an IC die that may assist temperature control of the IC die when in operation. The temperature control element may include a heat dissipation material disposed therein to assist dissipating thermal energy generated by the plurality of devices in the IC die during operation.

Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.

Abstract: The present disclosure relates to a polishing slurry composition and to a polishing slurry composition including nanoceria abrasive particles and a water-soluble compound including an intramolecular hydrophilic group, and further selectively including at least one from among an amphoteric compound including an intramolecular carboxyl group and amine group, a surface modifier including an organic acid, and a pH adjuster.

Abstract: A method for producing a lead-free X-ray shielding material using a bismuth halide compound is provided, the method including a first step of producing porous PDMS (Polydimethylsiloxane); a second step of producing a mixed solution of the bismuth halide compound and THF; and a third step of immersing the porous PDMS into the mixed solution such that the bismuth halide compound is loaded into the porous PDMS to produce a bismuth halide compound-PDMS composite material.

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

Abstract: A method for producing a lead-free X-ray shielding material using bismuth iodide is provided, the method including a first step of producing porous PDMS (Polydimethylsiloxane); a second step of producing a mixed solution of BiI3 and THF; and a third step of immersing the porous PDMS into the mixed solution such that the BiI3 is loaded into the porous PDMS to produce a BiI3-PDMS composite material.

Abstract: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may be formed as an integral part of an IC die that may assist temperature control of the IC die when in operation. The temperature control element may include a heat dissipation material disposed therein to assist dissipating thermal energy generated by the plurality of devices in the IC die during operation.

Abstract: A voltage regulator having a multiple of main stages and at least one accelerated voltage regulator (AVR) bridge is provided. The main stages may respond to low frequency current transients and provide DC output voltage regulation. The AVR bridges are switched much faster than the main stages and respond to high frequency current transients without regulating the DC output voltage. The AVR bridge frequency response range can overlap with the main stage frequency response range, and the lowest frequency to which the AVR bridges respond may be set lower than the highest frequency to which the main stages respond.

Abstract: A microelectronic system may include a microelectronic component having electrically conductive elements exposed at a first surface thereof, a socket mounted to a first surface of the microelectronic component and including a substrate embedded therein, one or more microelectronic elements each having active semiconductor devices therein and each having element contacts exposed at a front face thereof, and a plurality of socket pins mounted to and extending above the substrate, the socket pins being ground shielded coaxial socket pins. The one or more microelectronic elements may be disposed at least partially within a recess defined within the socket. The socket may have a land grid array comprising top surfaces of the plurality of the socket pins or electrically conductive pads mounted to corresponding ones of the socket pins, and the element contacts of the one or more microelectronic elements may be pressed into contact with the land grid array.

Abstract: Disclosed herein are a method, an apparatus and a storage medium for encoding/decoding using a transform-based feature map. An optimal basis vector is extracted from one or more feature maps, and a transform coefficient is acquired through a transform using the basis vector. The basis vector and the transform coefficient may be transmitted through a bitstream. In an embodiment, one or more feature maps are reconstructed using the basis vector and the transform coefficient, which are decoded from the bitstream.

Abstract: An apparatus and a method for measuring the RPM of a fan by using an IR-UWB radar are disclosed. The disclosed apparatus comprises: a radar signal variance acquisition unit which receives a reflected signal of an IR-UWB radar to acquire the variance of a signal at each location; a fan location acquisition unit for acquiring a first location and a second location, associated with the location of a fan, by using the variance of the signal at each location; an FFT calculation unit which performs FFT calculation for the signal of the first location to acquire a first FFT signal and which performs FFT calculation for the signal of the second location to acquire a second FFT signal; a subtraction unit for subtracting the second FFT signal from the first FFT signal; and an RPM acquisition unit for acquiring the RPM of the fan by using the signal subtracted by the subtraction unit.