Abstract: An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.

Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.

Abstract: The present disclosure relates to a vertical bipolar junction transistor. A vertical bipolar junction transistor includes a high concentration doping region emitter terminal disposed on a semiconductor substrate; a high concentration doping region collector terminal disposed on a semiconductor substrate; a high concentration doping region base terminal disposed between the emitter terminal and the collector terminal; a drift region having a first doping concentration surrounding the emitter terminal and being deeper than either the base terminal or the collector terminal; a base layer disposed below the drift region; a collector layer in contact with the base layer, the collector layer having a second doping concentration higher than the first doping concentration. The manufacturing cost of the vertical bipolar junction transistor can be lowered and a current gain can be elevated using a low-cost BCD process.

Abstract: The present invention provides a carbon fiber reinforced polypropylene resin composition with improved molding property. In particular, provided is a carbon fiber reinforced polypropylene resin composition with significantly improved molding property, tensile strength, flexural strength and the like by adding a modified polypropylene grafted with maleic anhydride as a compatibilizer to a polypropylene resin to reinforce the carbon fiber.

Abstract: There is provided an electrode pad including: a connection terminal part; a first plating layer including palladium phosphorus (Pd—P) formed on the connection terminal part; and a second plating layer including palladium (Pd) formed on the first plating layer.

Abstract: A printed circuit board includes an insulating layer; a metal pad formed on the insulating layer; a surface treatment layer formed on the metal pad; a solder layer formed on the surface treatment layer and the insulating layer; and an intermetallic compound layer formed between the solder layer and the surface treatment layer. Further, a printed circuit board may include an insulating layer; a metal seed layer formed on the insulating layer; a metal pad formed on the metal seed layer; a surface treatment layer formed on the metal pad and the metal seed layer; a solder layer formed on the surface treatment layer of the metal pad and the surface treatment layer of the metal seed layer; and an intermetallic compound layer formed between the solder layer and the surface treatment layer.

Abstract: There is provided an electrode pad including: a connection terminal part; a first plating layer including palladium phosphorus (Pd—P) formed on the connection terminal part; and a second plating layer including palladium (Pd) formed on the first plating layer.

Abstract: There is provided a method of forming a gold thin film, the method including: forming a nickel plating layer on a surface of an object through electroless nickel (Ni) plating; forming a palladium-copper mixture plating layer on the nickel plating layer through electroless plating using a palladium-copper (Pd—Cu) mixture; and forming a first gold thin film by immersing the palladium-copper mixture plating layer in a gold (Au) galvanic electrolytic liquid to replace a portion of copper (Cu) particles in the palladium-copper mixture plating layer with gold particles through a replacement reaction.

Abstract: A circuit board includes a circuit pattern formed on a substrate, a first solder resist layer formed on the circuit pattern, an electroless plating layer formed on the circuit pattern on which the first solder resist layer is opened, and a second solder resist layer formed on the first solder resist layer, and a method for manufacturing the same. According to certain embodiments, it is possible to cover a portion which has vulnerable plating quality due to solder resist residue or insufficient wetting around an edge of an existing solder resist layer by including an additional solder resist layer on a surface-treated plating layer. Further, it is possible to protect an undercut portion under the solder resist layer by forming the additional solder resist layer.

Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same. The printed circuit board includes: a copper pad surface roughness-treated to have a surface roughness of 0.1 to 1.0 ?m pitch period; and an electroless surface treatment plating layer formed on the copper pad. According to the present invention, when the copper pad has a surface roughness of a predetermined pitch period, the electroless surface treatment plating layer formed on the copper pad also has a surface roughness of the predetermined pitch period, thereby having an effect of widening a surface area and improving workability at the time of a wire bonding process for connection with an external device.

Abstract: Disclosed herein are an electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein each of the electroless nickel, palladium, and gold plated coatings has a thickness of 0.02 to 1 ?m, 0.01 to 0.3 ?m, and 0.01 to 0.5 ?m. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 ?m, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.

Abstract: Disclosed herein is a carrier for manufacturing a substrate, including: an insulation layer including a first metal layer formed on one side or both sides thereof; a second metal layer formed on one side of the first metal layer; and a third metal layer formed on one side of the second metal layer, wherein the second metal layer has a lower melting point than the first metal layer or the third metal layer. The carrier is advantageous in that a build up layer can be separated from a carrier by heating, so that a routing process is not required, with the result that the size of a substrate does not change when the build up layer is separated from the carrier, thereby reusing the carrier and maintaining the compatibility between the substrate and manufacturing facilities.

Abstract: Disclosed herein is a carrier for manufacturing a substrate, including: two insulation layers, each being provided on one side thereof with a first metal layer and on the other side thereof with a second metal layer; and a third metal layer having a lower melting point than the first metal layer and formed between the two first metal layers respectively formed on the two insulation layers such that the two first metal layers are attached to each other. The carrier is advantageous in that the carrier can be separated by heating the third metal layer, so that the size of a substrate does not change at the time of separating the carrier, thereby maintaining the compatibility between a substrate and manufacturing facilities.

Abstract: Disclosed herein is a carrier for manufacturing a substrate, including: an insulation layer including a first metal layer formed on one side or both sides thereof; a second metal layer formed on one side of the first metal layer; and a third metal layer formed on one side of the second metal layer, wherein the second metal layer has a lower melting point than the first metal layer or the third metal layer. The carrier is advantageous in that a build up layer can be separated from a carrier by heating, so that a routing process is not required, with the result that the size of a substrate does not change when the build up layer is separated from the carrier, thereby reusing to the carrier and maintaining the compatibility between the substrate and manufacturing facilities.

Abstract: Disclosed herein is a carrier for manufacturing a substrate, including: an insulation layer including a first metal layer formed on one side or both sides thereof; a second metal layer formed on one side of the first metal layer; and a third metal layer formed on one side of the second metal layer, wherein the second metal layer has a lower melting point than the first metal layer or the third metal layer. The carrier is advantageous in that a build up layer can be separated from a carrier by heating, so that a routing process is not required, with the result that the size of a substrate does not change when the build up layer is separated from the carrier, thereby reusing the carrier and maintaining the compatibility between the substrate and manufacturing facilities.

Abstract: Disclosed herein is a carrier for manufacturing a substrate, including: two insulation layers, each being provided on one side thereof with a first metal layer and on the other side thereof with a second metal layer; and a third metal layer having a lower melting point than the first metal layer and formed between the two first metal layers respectively formed on the two insulation layers such that the two first metal layers are attached to each other. The carrier is advantageous in that the carrier can be separated by heating the third metal layer, so that the size of a substrate does not change at the time of separating the carrier, thereby maintaining the compatibility between a substrate and manufacturing facilities.