Abstract: A thin film transistor and a method of manufacturing the same, and a display device and a method of manufacturing the same are disclosed, in which the thin film transistor substrate comprises an active layer formed on a substrate; a gate electrode controlling electron transfer within the active layer; a source electrode connected with one end area of the active layer; a drain electrode connected with the other end area of the active layer; and a light-shielding layer formed under the active layer to shield light from entering the active layer.

Abstract: A thin film transistor and a method of manufacturing the same, and a display device and a method of manufacturing the same are disclosed, in which the thin film transistor substrate comprises an active layer formed on a substrate; a gate electrode controlling electron transfer within the active layer; a source electrode connected with one end area of the active layer; a drain electrode connected with the other end area of the active layer; and a light-shielding layer formed under the active layer to shield light from entering the active layer.

Abstract: A method of fabricating an array substrate for an organic electroluminescent device includes forming a semiconductor layer of polysilicon in an element region, and a semiconductor pattern of polysilicon in a storage region on a substrate; forming a multiple-layered gate electrode corresponding to a center portion of the semiconductor layer and a first storage electrode corresponding to the semiconductor pattern; performing an impurity-doping to make a portion of the semiconductor layer not covered by the gate electrode into an ohmic contact layer and make the semiconductor pattern into a second storage electrode; forming source and drain electrodes and a third storage electrode corresponding to the first storage electrode; forming a first electrode contacting the drain electrode and a fourth storage electrode corresponding to the third storage electrode.

Abstract: A method of manufacturing a display device includes forming a gate electrode on a substrate, a gate insulating layer on the gate electrode, and an active layer on the gate insulating layer, the gate electrode made of extrinsic polycrystalline silicon, the active layer made of intrinsic polycrystalline silicon; forming an etch stopper on the active layer; forming source and drain electrodes spaced apart from each other on the etch stopper; forming an ohmic contact layer each between a side of the active layer and the source electrode and between an opposing side of the active layer and the drain electrode; forming a gate line connected to the gate electrode; and forming a data line crossing the gate line.

Abstract: An array substrate for a display device includes a gate electrode on a substrate; a gate insulating layer on the gate electrode and having the same plane area and the same plane shape as the gate electrode; an active layer on the gate insulating layer and exposing an edge of the gate insulating layer; an interlayer insulating layer on the active layer and including first and second active contact holes, the first and second active contact holes respectively exposing both sides of the active layers; first and second ohmic contact layers contacting the active layer through the first and second active contact holes, respectively; a source electrode on the first ohmic contact layer; a drain electrode on the second ohmic contact layer; a data line on the interlayer insulating layer and connected to the source electrode; a first passivation layer on the source electrode, the drain electrode and the data line, the first passivation layer, the interlayer insulating layer and the gate insulating layer have a first gat

Abstract: A method of fabricating an array substrate for an organic electroluminescent device includes forming a semiconductor layer of polysilicon in an element region, and a semiconductor pattern of polysilicon in a storage region on a substrate; forming a multiple-layered gate electrode corresponding to a center portion of the semiconductor layer and a first storage electrode corresponding to the semiconductor pattern; performing an impurity-doping to make a portion of the semiconductor layer not covered by the gate electrode into an ohmic contact layer and make the semiconductor pattern into a second storage electrode; forming source and drain electrodes and a third storage electrode corresponding to the first storage electrode; forming a first electrode contacting the drain electrode and a fourth storage electrode corresponding to the third storage electrode.

Abstract: A light emitting device and a method of manufacturing the same are provided.

Abstract: A method of manufacturing a display device includes forming a gate electrode on a substrate, a gate insulating layer on the gate electrode, and an active layer on the gate insulating layer, the gate electrode made of extrinsic polycrystalline silicon, the active layer made of intrinsic polycrystalline silicon; forming an etch stopper on the active layer; forming source and drain electrodes spaced apart from each other on the etch stopper; forming an ohmic contact layer each between a side of the active layer and the source electrode and between an opposing side of the active layer and the drain electrode; forming a gate line connected to the gate electrode; and forming a data line crossing the gate line.

Abstract: A method of manufacturing a display device includes forming a gate electrode on a substrate, a gate insulating layer on the gate electrode, and an active layer on the gate insulating layer, the gate electrode made of extrinsic polycrystalline silicon, the active layer made of intrinsic polycrystalline silicon; forming an etch stopper on the active layer; forming source and drain electrodes spaced apart from each other on the etch stopper; forming an ohmic contact layer each between a side of the active layer and the source electrode and between an opposing side of the active layer and the drain electrode; forming a gate line connected to the gate electrode; and forming a data line crossing the gate line.

Abstract: A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of th

Abstract: An array substrate for a display device includes a gate electrode on a substrate; a gate insulating layer on the gate electrode and having the same plane area and the same plane shape as the gate electrode; an active layer on the gate insulating layer and exposing an edge of the gate insulating layer; an interlayer insulating layer on the active layer and including first and second active contact holes, the first and second active contact holes respectively exposing both sides of the active layers; first and second ohmic contact layers contacting the active layer through the first and second active contact holes, respectively; a source electrode on the first ohmic contact layer; a drain electrode on the second ohmic contact layer; a data line on the interlayer insulating layer and connected to the source electrode; a first passivation layer on the source electrode, the drain electrode and the data line, the first passivation layer, the interlayer insulating layer and the gate insulating layer have a first gat

Abstract: A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.

Abstract: A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.

Abstract: A method of fabricating an array substrate includes forming a buffer layer; forming a gate electrode on the buffer layer, a gate insulating layer on the gate electrode and an active layer on the gate insulating layer, the gate electrode including a bottom pattern, a middle pattern and a top pattern; forming an interlayer insulating layer, the first and second contact holes respectively exposing both sides of the active layer; forming first and second barrier patterns, first and second ohmic contact patterns, a source electrode, a drain, and a data line; forming a first passivation layer including a gate contact hole exposing the gate electrode; forming a gate line on the first passivation layer and contacting the gate electrode through the gate contact hole; forming a second passivation layer on the gate line; and forming a pixel electrode on the second passivation layer and contacting the drain electrode.

Abstract: A method of manufacturing a display device includes forming a gate electrode on a substrate, a gate insulating layer on the gate electrode, and an active layer on the gate insulating layer, the gate electrode made of extrinsic polycrystalline silicon, the active layer made of intrinsic polycrystalline silicon; forming an etch stopper on the active layer; forming source and drain electrodes spaced apart from each other on the etch stopper; forming an ohmic contact layer each between a side of the active layer and the source electrode and between an opposing side of the active layer and the drain electrode; forming a gate line connected to the gate electrode; and forming a data line crossing the gate line.

Abstract: A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of th

Abstract: A light emitting device and a method of manufacturing the same are provided.

Abstract: A light emitting device and a method of manufacturing the same are provided.

Abstract: A TFT having a dual buffer structure, a method of fabricating the same, and a flat panel display having the TFT, and a method of fabricating the same are provided. The TFT includes a first buffer layer formed of an amorphous silicon layer on a substrate, a second buffer layer formed on the first buffer layer. The TFT also includes a semiconductor layer formed on the second buffer layer and a gate electrode formed on the semiconductor layer. The dual buffer structure provides better barrier to impurities diffusing from the substrate, and also acts as a black matrix to reduce unwanted reflections and is a source of hydrogen to passivate other layers.

Abstract: An in-plane switching mode liquid crystal display device includes first and second substrates. A plurality of gate and data bus lines define pixel regions and arranged on the first substrate. A plurality of thin film transistors are adjacent respective cross points of the gate and data bus lines. A plurality of gate electrodes are connected to said gate bus lines. A gate insulator is on the gate electrodes and a first metal layer includes a plurality of first electrodes on the gate insulator. A passivation layer is on the first metal layer. A transparent second metal layer includes a plurality of second electrodes on the passivation layer, the first and second electrodes applying plane electric fields.