Patents by Inventor Seong-ook Jung

Seong-ook Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12106797
    Abstract: A bit line sense amplifier includes: a first inverter having an input terminal connected to a first sensing node and an output terminal connected to a second inner bit line; a second inverter having an input terminal connected to a second sensing node and an output terminal connected to a first inner bit line; a first capacitor connected between the first sensing node and the first inner bit line; a second capacitor connected between the second sensing node and the second inner bit line; an isolation unit configured to cut off a connection between the first inner bit line and a second bit line; and an offset cancellation unit configured to connect the first sensing node to the second inner bit line, the first inner bit line to the first bit line, the second sensing node to the first inner bit line, and the second inner bit line to the second bit line.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: October 1, 2024
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, In Jun Jung, Tae Hyun Kim
  • Patent number: 12087344
    Abstract: Exemplary embodiments provide a sensing amplifier based flip-flop applying a nonvolatile memory device which is applicable to a mobile device which has a small hardware area, uses a small control signal, does not include a separate write circuit, has low writing power consumption, a short reading time and small power consumption, and requires a low power operation.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: September 10, 2024
    Assignee: UIF (University Industry Foundation), Yonsei University
    Inventors: Seong Ook Jung, Se Keon Kim, Tae Woo Oh, Se Hee Lim, Dong Han Ko
  • Publication number: 20240220853
    Abstract: There is provided a method of training a multi-layer perceptron on a read access yield of a static random access memory (SRAM), the method including: a first training operation of performing training with a design parameter of the SRAM according to a read operation metric of the SRAM, training data according to the read operation metric of the SRAM, and a transistor level simulation result of the SRAM; a second training operation of performing training with the design parameter of the SRAM according to the read operation metric of the SRAM, the training data according to the read operation metric of the SRAM, and a layout level simulation result of the SRAM; and a third training operation of performing training with the design parameter of the SRAM according to the read operation metric of the SRAM, the training data according to the read operation metric of the SRAM, and a measurement result measured with a chip in which the SRAM is formed.
    Type: Application
    Filed: February 16, 2023
    Publication date: July 4, 2024
    Applicant: UIF (University Industry Foundation), Yonsei University
    Inventors: Seong Ook JUNG, Sung Ho PARK, Gi Seok KIM, Won Joon JO
  • Patent number: 11955155
    Abstract: A nonvolatile memory device according to the embodiment includes: a first inverter; and a second inverter cross-coupled to the first inverter, wherein the second inverter includes a pull-up transistor, a pull-down transistor, and a ferroelectric field effect transistor having gate nodes connected to each other, and a restore transistor having one electrode connected to the ferroelectric field effect transistor, and the second inverter stores data in a nonvolatile manner.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: April 9, 2024
    Assignee: UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, Se Keon Kim, Tae Woo Oh, Se Hee Lim, Dong Han Ko
  • Patent number: 11955157
    Abstract: A PUF apparatus comprises: a PUF cell array in which a plurality of PUF cells are arranged each including a FeFET pair whose gates are commonly connected to a corresponding word line among a plurality of word lines, and whose drains and sources are connected to a corresponding bit line pair and a corresponding source line pair among a plurality of bit line pairs and a plurality of source line pairs running in a direction crossing the plurality of word lines; and a read-write-back block which is activated according to a read enable signal, and senses and amplifies a voltage difference occurring in a corresponding bit line pair among the plurality of bit line pairs according to the difference in driving strength due to a deviation in a manufacturing process of the FeFET pair in the PUF cell selected by a selected word line among the plurality of word lines.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 9, 2024
    Assignee: INDUSTRY-ACADEMIC CORPORATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, Se Hee Lim, Tae Woo Oh, Se Keon Kim, Dong Han Ko
  • Patent number: 11928588
    Abstract: Disclosed is an in-memory device for operation of a multi-bit weight. A multi-bit memory cell array according to an exemplary embodiment of the present invention includes at least one multi-bit unit which stores input data based on an input signal and outputs a per-group sum value summed for every group by applying a multi-bit weight to the stored input data; and a final summation unit which is connected to at least one multi-bit unit, adjusts a ratio for every group to receive the peer-group sum value, and outputs a final output value by summing the input per-group sum value.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: March 12, 2024
    Assignee: UIF (University Industry Foundation), Yonsei University
    Inventors: Seong Ook Jung, Hong Keun Ahn, Young Kyu Lee
  • Publication number: 20240048132
    Abstract: A flip-flop includes an input logic circuit, a first latch, a second latch, and an output multiplexer; where the input logic circuit outputs a clock bar signal based on an input data bit and a clock signal, where the first latch and the second latch operate based on the input data bit, the clock signal, and a clock bar signal, where the output multiplexer operates based on outputs from nodes of the first and second nodes and outputs an output data bit, and where the input logic circuit has a uniform value in a period where there is no change of a value of the output data bit.
    Type: Application
    Filed: June 7, 2023
    Publication date: February 8, 2024
    Applicants: SAMSUNG ELECTRONICS CO., LTD., UIF (University Industry Foundation), Yonsel university
    Inventors: SEONG-OOK JUNG, SE KEON KIM, HYUNJUN KIM, KYEONG RIM BAEK, KEONHEE CHO
  • Publication number: 20240036827
    Abstract: There is provided a computation apparatus located in a memory module and configured to perform computation with data stored in the memory, the computation apparatus including: a plurality of word lines to which an input is provided; a plurality of unit arrays which store a weight having a sign and perform a multiplication operation on the input provided from the word line and the weight; and an accumulation line connected to the plurality of unit arrays and on which results of the multiplication operations performed by the plurality of unit arrays are accumulated, wherein each of the plurality of unit arrays includes a source follower amplifier including a ferroelectric transistor configured to output a voltage corresponding to a result of the multiplication operation with respect to an input voltage provided to the word line.
    Type: Application
    Filed: February 16, 2023
    Publication date: February 1, 2024
    Applicant: UIF (University Industry Foundation), Yonsei University
    Inventors: Seong Ook JUNG, Dong Han KO, Young Kyu LEE, Se Hee LIM
  • Publication number: 20230385024
    Abstract: A memory cell comprises: a weight storage circuit configured, when a write word line is activated, to receive a weight voltage, according to a weight value to be stored through a write bit line, and transmit the weight voltage to a storage node, and, when a read word line is activated, to drop a read voltage precharged, according to a voltage level of the storage node, to a voltage level of the read word line; and a MAC operation circuit configured, when a data enable line is activated, to transmit an input voltage according to a value of input data to a coupling node through a data input line, and, to discharge the coupling node according to a level of the weight voltage stored in the storage node, and, when the data enable line is reactivated, to transmit a voltage change of the coupling node to a multiply word line.
    Type: Application
    Filed: May 4, 2023
    Publication date: November 30, 2023
    Inventors: Seong-Ook JUNG, Do-Han KIM, In-Jun JUNG
  • Publication number: 20230377639
    Abstract: An SRAM comprises: a memory cell array in which a plurality of memory cells each defined by a word line and a bit line pair are arranged; a write driver that applies a write voltage corresponding to the applied data to a bit line pair connected to the memory cell; and a word line driver activating the word line after the write voltage is applied to the bit line pair and after a pre-develop period.
    Type: Application
    Filed: February 14, 2023
    Publication date: November 23, 2023
    Inventors: Seong Ook JUNG, Keon Hee CHO, Ji Sang OH, Min June YEO
  • Patent number: 11790971
    Abstract: A ferroelectric random access memory device comprises: a memory cell array including a plurality of memory cells each having one ferroelectric transistor (FeFET) connected between a read line of a plurality of read lines and a source line of a plurality of source lines and one transistor connected between a bit line of a plurality of bit lines and a gate of the FeFET and having a gate connected to a corresponding word line of a plurality of word lines; and a read/write control unit, when address information for a memory cell to be written is applied with a write command and data, selecting a word line and a read line corresponding to a row address and applying a write voltage having a positive voltage level, and applying a ground voltage to the selected read line, and applying the write voltage to a bit line corresponding to a memory cell.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: October 17, 2023
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, Dong Han Ko, Tae Woo Oh, Se Hee Lim, Se Keon Kim
  • Publication number: 20230086821
    Abstract: A content addressable memory based on a self-rectifying ferroelectric tunnel junction element comprises: a cell array unit having a plurality of TCAM cells, each comprising two self-rectifying ferroelectric tunnel junction elements (SR-FTJ) connected between a corresponding match line of a plurality of match lines extending in a first direction and a corresponding bit line pair of a plurality of bit line pairs extending in a second direction; a precharge unit precharging a corresponding match line of the plurality of match lines to a power supply voltage level in response to a precharge signal; and a data input/output unit having a plurality of access transistor pairs electrically connecting or disconnecting a corresponding bit line pair among the plurality of bit line pairs and a source line, in response to a voltage applied through a corresponding search line pair among a plurality of search line pairs according to data to be written or searched.
    Type: Application
    Filed: September 17, 2022
    Publication date: March 23, 2023
    Inventors: Seong Ook JUNG, Se Hee LIM
  • Patent number: 11587203
    Abstract: A method for optimizing a hardware structure of a convolutional neural network including: searching an initial feature value group by which a final convolution layer located at a final stage among a plurality of convolution layers, setting an initial fusing network by analyzing a feature value group having a size corresponding to the initial feature value group; computing an operation time for each layer by allocating the number of operators corresponding to the size of the feature value group to each of the plurality of convolution layers, and dividing the size of the feature value group by determining a layer having a minimum operation time; resetting the fusing network by changing the size of the feature value group, determining the size of the feature value group having the smallest number of operators, determining the number of operators to be included in each of the plurality of convolution layers.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: February 21, 2023
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, Su Min Lee, Sung Hwan Joo
  • Publication number: 20230036684
    Abstract: A bit line sense amplifier includes: a first inverter having an input terminal connected to a first sensing node and an output terminal connected to a second inner bit line; a second inverter having an input terminal connected to a second sensing node and an output terminal connected to a first inner bit line; a first capacitor connected between the first sensing node and the first inner bit line; a second capacitor connected between the second sensing node and the second inner bit line; an isolation unit configured to cut off a connection between the first inner bit line and a second bit line; and an offset cancellation unit configured to connect the first sensing node to the second inner bit line, the first inner bit line to the first bit line, the second sensing node to the first inner bit line, and the second inner bit line to the second bit line.
    Type: Application
    Filed: July 7, 2022
    Publication date: February 2, 2023
    Inventors: Seong Ook JUNG, In Jun JUNG, Tae Hyun KIM
  • Patent number: 11521679
    Abstract: Disclosed is a memory device for cancelling a sneak current. The memory device according to the exemplary embodiment of the present disclosure includes a memory cell array which includes a plurality of word lines and a plurality of bit lines intersecting each other and memory cells disposed at intersections of the word lines and the bit lines; and a sensing circuit which supplies a bit line current to all or some of the bit lines, cancels a sneak current based on the bit line current by at least one switching control, and senses and amplifies data stored in the memory cell to output the sensed and amplified data.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 6, 2022
    Assignee: UIF (University Industry Foundation), Yonsei University
    Inventors: Seong Ook Jung, Tae Hyun Kim, Byung Kyu Song
  • Publication number: 20220383926
    Abstract: Exemplary embodiments provide a sensing amplifier based flip-flop applying a nonvolatile memory device which is applicable to a mobile device which has a small hardware area, uses a small control signal, does not include a separate write circuit, has low writing power consumption, a short reading time and small power consumption, and requires a low power operation.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 1, 2022
    Inventors: Seong Ook JUNG, Se Keon KIM, Tae Woo OH, Se Hee LIM, Dong Han KO
  • Publication number: 20220383927
    Abstract: A PUF apparatus comprises: a PUF cell array in which a plurality of PUF cells are arranged each including a FeFET pair whose gates are commonly connected to a corresponding word line among a plurality of word lines, and whose drains and sources are connected to a corresponding bit line pair and a corresponding source line pair among a plurality of bit line pairs and a plurality of source line pairs running in a direction crossing the plurality of word lines; and a read-write-back block which is activated according to a read enable signal, and senses and amplifies a voltage difference occurring in a corresponding bit line pair among the plurality of bit line pairs according to the difference in driving strength due to a deviation in a manufacturing process of the FeFET pair in the PUF cell selected by a selected word line among the plurality of word lines.
    Type: Application
    Filed: February 14, 2022
    Publication date: December 1, 2022
    Inventors: Seong Ook JUNG, Se Hee LIM, Tae Woo OH, Se Keon KIM, Dong Han KO
  • Publication number: 20220254398
    Abstract: A nonvolatile memory device according to the embodiment includes: a first inverter; and a second inverter cross-coupled to the first inverter, wherein the second inverter includes a pull-up transistor, a pull-down transistor, and a ferroelectric field effect transistor having gate nodes connected to each other, and a restore transistor having one electrode connected to the ferroelectric field effect transistor, and the second inverter stores data in a nonvolatile manner.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 11, 2022
    Inventors: Seong Ook JUNG, Se Keon KIM, Tae Woo OH, Se Hee LIM, Dong Han KO
  • Patent number: 11403731
    Abstract: Disclosed is an image upscaling apparatus that includes: multiple convolution layers, each configured to receive an input image or a feature map outputted by a previous convolution layer and extract features to output a feature map; and a multilayer configured to receive a final feature map outputted from the last convolution layer and output an upscaled output image. The multilayer includes: a first partition layer including first filters having a minimum size along the x-axis and y-axis directions and the same size as the final feature map along the z-axis direction; and at least one second partition layer, each including second filters, having a size greater than that of the first filter in the x-axis and y-axis directions and having a number and size of the first filter in the z-axis direction, and configured to shuffle features in the x-axis and y-axis directions of the first shuffle map.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: August 2, 2022
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, Sung Hwan Joo, Su Min Lee
  • Publication number: 20220215870
    Abstract: A ferroelectric random access memory device comprises: a memory cell array including a plurality of memory cells each having one ferroelectric transistor (FeFET) connected between a read line of a plurality of read lines and a source line of a plurality of source lines and one transistor connected between a bit line of a plurality of bit lines and a gate of the FeFET and having a gate connected to a corresponding word line of a plurality of word lines; and a read/write control unit, when address information for a memory cell to be written is applied with a write command and data, selecting a word line and a read line corresponding to a row address and applying a write voltage having a positive voltage level, and applying a ground voltage to the selected read line, and applying the write voltage to a bit line corresponding to a memory cell.
    Type: Application
    Filed: January 4, 2022
    Publication date: July 7, 2022
    Inventors: Seong Ook JUNG, Dong Han KO, Tae Woo OH, Se Hee LIM, Se Keon KIM