Abstract: In a sense amplifier, a current amplifier outputs a first and a second voltage signal in response to a first control signal. The first and second voltage signals are output based on a detected current difference between a pair of input/output lines. A voltage amplifier generates a third and a fourth voltage signal based on a detected voltage difference between the first and second voltage signals. The third and a fourth voltage signals are generated in response to a second control signal. A first latch circuit latches the third and fourth voltage signals, and outputs a first output signal in response to the second control signal. A second latch circuit latches the first and second voltage signals and outputs a second output signal in response to a third control signal. An output circuit performs a logic operation on the first output signal and the second output signal, and outputs a result of the logic operation as a resultant signal.

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract: A test method and apparatus for a semiconductor memory device is characterized by the sequentially programmed use of two test different modes. A first test mode tests at least signal line integrity for the semiconductor memory device by testing a merged set of bits line. The second test mode further tests at least signal line integrity after first separating the merged bits lines. Logical combination of test data derived from the first and second test modes are used to generate error detection signals. At least one bit line associated with a parity bit is preferable merged and separated in the foregoing approach.

Abstract: An apparatus for controlling a rotation angle of a camera module of a mobile communication device includes: a camera module, a driving force generating means having a rotation shaft, a push member rotatably coupled to the rotation shaft, a camera rotating plate fixed to the camera module, a pivot member for connecting the push member to the camera rotating plate and serving as a pivot for the camera rotating plate, the driving force generating means driving the push member via the rotation shaft for selectively pushing the camera rotating plate to control a rotation angle of the camera module, a boss formed at the center of the camera rotating plate and having a coupling cavity at its central portion, and a projection connected to the rotation shaft of the driving force generating means so as to be inserted in the coupling cavity of the boss.

Abstract: In a sense amplifier, a current amplifier outputs a first and a second voltage signal in response to a first control signal. The first and second voltage signals are output based on a detected current difference between a pair of input/output lines. A voltage amplifier generates a third and a fourth voltage signal based on a detected voltage difference between the first and second voltage signals. The third and a fourth voltage signals are generated in response to a second control signal. A first latch circuit latches the third and fourth voltage signals, and outputs a first output signal in response to the second control signal. A second latch circuit latches the first and second voltage signals and outputs a second output signal in response to a third control signal. An output circuit performs a logic operation on the first output signal and the second output signal, and outputs a result of the logic operation as a resultant signal.

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract: Example embodiments are directed to a semiconductor memory device having a hierarchical input/output (I/O) line structure. The semiconductor memory device may include a plurality of core blocks, with each core block including a plurality of memory banks sharing an input/output sense amplifier. Data input/output lines may be arranged on each of the plurality of core blocks.

Abstract: A test method and apparatus for a semiconductor memory device is characterized by the sequentially programmed use of two test different modes. A first test mode tests at least signal line integrity for the semiconductor memory device by testing a merged set of bits line. The second test mode further tests at least signal line integrity after first separating the merged bits lines. Logical combination of test data derived from the first and second test modes are used to generate error detection signals. At least one bit line associated with a parity bit is preferable merged and separated in the foregoing approach.

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract: An apparatus for controlling a rotation angle of a camera module of a mobile communication device includes: a camera module, a driving force generating means having a rotation shaft, a push member rotatably coupled to the rotation shaft, a camera rotating plate fixed to the camera module, a pivot member for connecting the push member to the camera rotating plate and serving as a pivot for the camera rotating plate, the driving force generating means driving the push member via the rotation shaft for selectively pushing the camera rotating plate to control a rotation angle of the camera module, a boss formed at the center of the camera rotating plate and having a coupling cavity at its central portion, and a projection connected to the rotation shaft of the driving force generating means so as to be inserted in the coupling cavity of the boss.

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.