Patents by Inventor Seong Hwan Jeon
Seong Hwan Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230206974Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal, a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.Type: ApplicationFiled: February 21, 2023Publication date: June 29, 2023Inventors: HYE-RAN KIM, SEONG-HWAN JEON, TAE-YOUNG OH
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Patent number: 11615825Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.Type: GrantFiled: January 31, 2022Date of Patent: March 28, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye-Ran Kim, Seong-Hwan Jeon, Tae-Young Oh
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Publication number: 20220157357Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: HYE-RAN KIM, SEONG-HWAN JEON, TAE-YOUNG OH
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Patent number: 11282555Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.Type: GrantFiled: March 3, 2021Date of Patent: March 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye-Ran Kim, Seong-Hwan Jeon, Tae-Young Oh
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Publication number: 20210183420Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.Type: ApplicationFiled: March 3, 2021Publication date: June 17, 2021Inventors: HYE-RAN KIM, SEONG-HWAN JEON, TAE-YOUNG OH
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Patent number: 10943630Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.Type: GrantFiled: December 31, 2019Date of Patent: March 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye-Ran Kim, Seong-Hwan Jeon, Tae-Young Oh
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Patent number: 10937466Abstract: A semiconductor package with clock sharing, which is suitable for an electronic system having low power consumption characteristics, is provided. The semiconductor package includes a lower package including a lower package substrate and a memory controller mounted on the lower package substrate, an upper package stacked on the lower package and including an upper package substrate and a memory device mounted on the upper package substrate, and a plurality of vertical interconnections electrically connecting the lower package to the upper package. The semiconductor package is configured to cause the memory controller to output a first data clock signal used for a channel that is an independent data interface between the memory controller and the memory device, branch the first data clock signal, and provide the branched first data clock signal to the memory device.Type: GrantFiled: May 21, 2020Date of Patent: March 2, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Seong-hwan Jeon
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Publication number: 20200286531Abstract: A semiconductor package with clock sharing, which is suitable for an electronic system having low power consumption characteristics, is provided. The semiconductor package includes a lower package including a lower package substrate and a memory controller mounted on the lower package substrate, an upper package stacked on the lower package and including an upper package substrate and a memory device mounted on the upper package substrate, and a plurality of vertical interconnections electrically connecting the lower package to the upper package. The semiconductor package is configured to cause the memory controller to output a first data clock signal used for a channel that is an independent data interface between the memory controller and the memory device, branch the first data clock signal, and provide the branched first data clock signal to the memory device.Type: ApplicationFiled: May 21, 2020Publication date: September 10, 2020Applicant: Samsung Electronics Co., Ltd.Inventor: Seong-hwan JEON
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Patent number: 10714149Abstract: A semiconductor package with clock sharing, which is suitable for an electronic system having low power consumption characteristics, is provided. The semiconductor package includes a lower package including a lower package substrate and a memory controller mounted on the lower package substrate, an upper package stacked on the lower package and including an upper package substrate and a memory device mounted on the upper package substrate, and a plurality of vertical interconnections electrically connecting the lower package to the upper package. The semiconductor package is configured to cause the memory controller to output a first data clock signal used for a channel that is an independent data interface between the memory controller and the memory device, branch the first data clock signal, and provide the branched first data clock signal to the memory device.Type: GrantFiled: August 2, 2018Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Seong-hwan Jeon
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Patent number: 10692555Abstract: A method of operating a semiconductor memory device including a plurality of pins configured to transfer data and signals from/to an outside of the semiconductor memory device, a memory cell array and a control logic circuit to control access to the memory cell array. A write command synchronized with a main clock signal and data synchronized with a data clock signal are received from outside of the semiconductor memory device, the data is stored in the memory cell array based on a frequency-divided data clock signal, data is read from the memory cell array in response to a read command and a target address received from the outside of the semiconductor memory device, and the read data is transmitted to the outside of the semiconductor memory device selectively with a strobe signal generated based on a frequency of the main clock signal.Type: GrantFiled: January 16, 2019Date of Patent: June 23, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-Seok Oh, Seong-Hwan Jeon
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Publication number: 20200143858Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.Type: ApplicationFiled: December 31, 2019Publication date: May 7, 2020Inventors: Hye-Ran Kim, Seong-Hwan Jeon, Tae-Young Oh
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Patent number: 10553264Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.Type: GrantFiled: October 3, 2017Date of Patent: February 4, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye-Ran Kim, Seong-Hwan Jeon, Tae-Young Oh
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Publication number: 20190221240Abstract: A semiconductor package with clock sharing, which is suitable for an electronic system having low power consumption characteristics, is provided. The semiconductor package includes a lower package including a lower package substrate and a memory controller mounted on the lower package substrate, an upper package stacked on the lower package and including an upper package substrate and a memory device mounted on the upper package substrate, and a plurality of vertical interconnections electrically connecting the lower package to the upper package. The semiconductor package is configured to cause the memory controller to output a first data clock signal used for a channel that is an independent data interface between the memory controller and the memory device, branch the first data clock signal, and provide the branched first data clock signal to the memory device.Type: ApplicationFiled: August 2, 2018Publication date: July 18, 2019Applicant: Samsung Electronics Co., Ltd.Inventor: Seong-hwan JEON
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Publication number: 20190172512Abstract: A method of operating a semiconductor memory device including a plurality of pins configured to transfer data and signals from/to an outside of the semiconductor memory device, a memory cell array and a control logic circuit to control access to the memory cell array. A write command synchronized with a main clock signal and data synchronized with a data clock signal are received from outside of the semiconductor memory device, the data is stored in the memory cell array based on a frequency-divided data clock signal, data is read from the memory cell array in response to a read command and a target address received from the outside of the semiconductor memory device, and the read data is transmitted to the outside of the semiconductor memory device selectively with a strobe signal generated based on a frequency of the main clock signal.Type: ApplicationFiled: January 16, 2019Publication date: June 6, 2019Inventors: Ki-Seok OH, Seong-Hwan JEON
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Patent number: 10283186Abstract: A data alignment circuit of a semiconductor memory device including: a data sampling circuit configured to receive a data sequence and an internal data strobe signal, wherein the data sampling circuit samples the data sequence based on the internal data strobe signal to generate first and second data sequences; a division circuit configured to receive a clock signal and the internal data strobe signal, divide the clock signal to produce a divided clock signal and output an alignment control signal by sampling the divided clock signal based on the internal data strobe signal; and a data alignment block configured to receive the first and second data sequences, and the alignment control signal, and align the first and second data sequences in parallel to output internal data.Type: GrantFiled: October 18, 2017Date of Patent: May 7, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seong-Hwan Jeon, Kyung-Soo Ha, Jin-Seok Heo, In-Dal Song, Jung-Hwan Choi
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Patent number: 10186309Abstract: In a method of operating a semiconductor memory device including a memory cell array and a control logic circuit configured to control access to the memory cell array, data synchronized with a differential data clock signal is received from an external memory controller, the data is stored in the memory cell array based on a frequency-divided data clock signal from which the differential data clock signal is divided, data is read from the memory cell array in response to a read command and a target address from the memory controller, and the read data is transmitted to the memory controller with one of a single strobe signal and a differential strobe signal according to a strobe mode of the semiconductor memory device.Type: GrantFiled: June 15, 2017Date of Patent: January 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-Seok Oh, Seong-Hwan Jeon
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Publication number: 20180174636Abstract: A data alignment circuit of a semiconductor memory device including: a data sampling circuit configured to receive a data sequence and an internal data strobe signal, wherein the data sampling circuit samples the data sequence based on the internal data strobe signal to generate first and second data sequences; a division circuit configured to receive a clock signal and the internal data strobe signal, divide the clock signal to produce a divided clock signal and output an alignment control signal by sampling the divided clock signal based on the internal data strobe signal; and a data alignment block configured to receive the first and second data sequences, and the alignment control signal, and align the first and second data sequences in parallel to output internal data.Type: ApplicationFiled: October 18, 2017Publication date: June 21, 2018Inventors: SEONG-HWAN JEON, KYUNG-SOO HA, JIN-SEOK HEO, IN-DAL SONG, JUNG-HWAN CHOI
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Patent number: 9985619Abstract: A duty cycle corrector (DCC) includes a duty corrector circuit configured to adjust a duty of an input signal to output a duty-adjusted signal; a duty detector circuit configured to generate a correction code associated with the adjustment of the duty, based on a charge pump operation and a counting operation; and a timing controller configured to generate a first control signal associated with the charge pump operation and a second control signal associated with the counting operation in synchronization with a first clock.Type: GrantFiled: July 11, 2016Date of Patent: May 29, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoon Lee, Joung-wook Moon, Seong-hwan Jeon
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Publication number: 20180102151Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.Type: ApplicationFiled: October 3, 2017Publication date: April 12, 2018Inventors: Hye-Ran Kim, Seong-Hwan Jeon, Tae-Young Oh
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Publication number: 20180005686Abstract: In a method of operating a semiconductor memory device including a memory cell array and a control logic circuit configured to control access to the memory cell array, data synchronized with a differential data clock signal is received from an external memory controller, the data is stored in the memory cell array based on a frequency-divided data clock signal from which the differential data clock signal is divided, data is read from the memory cell array in response to a read command and a target address from the memory controller, and the read data is transmitted to the memory controller with one of a single strobe signal and a differential strobe signal according to a strobe mode of the semiconductor memory device.Type: ApplicationFiled: June 15, 2017Publication date: January 4, 2018Inventors: Ki-Seok OH, Seong-Hwan JEON