Abstract: According to exemplary methods and systems of the present principles, the location of defective field repairable units (FRUS) of a circuit that have varying sizes or varying numbers of scan cells may be identified by employing tiles including scan cells from different FRUS. A set of test patterns may be scanned through the scan cells such that cells belonging to FRUs within a tile may be concealed while analyzing the response of scan cells in the tile contributed by a different FRU. Further, defective tiles are discoverable at any tile location and in any quantity within a maximal capacity using a compressed signature. In addition, signature registers that process data at a rate that is faster than the scan shift rate of the circuit may be employed during compression to multiply a circuit response by a plurality of components of a compression matrix during one scan shift cycle.

Abstract: A method includes compressing control patterns describing values required at the control signals of blocking logic gates, by linear feedback shift register LFSR reseeding; bypassing blocking logic gates for some groups of scan chains that do not capture unknown values in output response of scan test patterns for testing circuits; and reducing numbers of specified bits in densely specified ones of the control patterns for further reducing the size of a seed of the LFSR.

Abstract: A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.

Abstract: According to exemplary methods and systems of the present principles, the location of defective field repairable units (FRUS) of a circuit that have varying sizes or varying numbers of scan cells may be identified by employing tiles including scan cells from different FRUS. A set of test patterns may be scanned through the scan cells such that cells belonging to FRUs within a tile may be concealed while analyzing the response of scan cells in the tile contributed by a different FRU. Further, defective tiles are discoverable at any tile location and in any quantity within a maximal capacity using a compressed signature. In addition, signature registers that process data at a rate that is faster than the scan shift rate of the circuit may be employed during compression to multiply a circuit response by a plurality of components of a compression matrix during one scan shift cycle.

Abstract: A system and method for integrated circuit diagnosis includes partitioning an integrated circuit design into sub-regions according to a structure of the integrated circuit design. A decision function is generated for a sub-region by training a machine learning tool. A sequence of test patterns is applied to a device under test (DUT) to determine responses. If the DUT fails, all the decision functions are evaluated with the errors produced by the DUT. A sub-region whose decision function yielded a highest value is selected to find a defect sub-region in the DUT.

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract: Implementations of the present principles are directed to test output compaction arrangements and a methods of generating control patterns for unknown blocking. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract: A method includes compressing control patterns describing values required at the control signals of blocking logic gates, by linear feedback shift register LFSR reseeding; bypassing blocking logic gates for some groups of scan chains that do not capture unknown values in output response of scan test patterns for testing circuits; and reducing numbers of specified bits in densely specified ones of the control patterns for further reducing the size of a seed of the LFSR.

Abstract: A test system for a circuit board , wherein the circuit board has a plurality of cores such that at least one of the plurality of cores is adapted to use a test protocol independent of a communication fabric used in the circuit board. A system-on-chip (SOC) with an embedded test protocol architecture, the SOC comprising at least one embedded core, a communication fabric that connects at least one embedded core, at least one test server; and at least one test client connected to said at least one embedded core and connected to the communication fabric.

Abstract: Determining a test point location in a structured application specific integrated circuit (ASIC) includes using one or more unused cells of the structured ASIC. In particular, an unused cell of the structured ASIC is identified and then a test point is inserted at the unused cell of the structured ASIC (e.g., if the unused cell is neighboring at least one used cell of the structured ASIC).

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract: A method for increasing fault coverage and compression with a broadcast scan-based test data compression circuit includes inserting test points for breaking correlations existing between scan inputs that belong to same scan slices making some faults un-testable with a broadcast scan-based test data compression circuit; and reordering scan inputs for further reducing correlations between scan inputs that belong to the same scan slices.

Abstract: A method includes selecting at least one regular scan cell that is replaced with a corresponding one of an enhanced scan cell in a scan chain for scan based delay testing of the digital circuit, controlling the enhanced scan cell with a skewed load approach, and controlling regular scan cells of the scan chain with a broadside approach. More specifically, this reduces test sequence lengths and achieves higher delay fault coverage, without having to pay high cost to drive all scan cells by the skewed load approach, which requires a faster switching than the broadside approach. No additional pins are required for driving enhanced scan cells because the drive signal for switching the enhanced scan cells is derived from the signal for driving the regular scan cells.

Abstract: A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.

Abstract: A spatial compactor design and technique for the compaction of test response data is herein disclosed which advantageously provides a scan-out response with multiple opportunities to be observed on different output channels in one to several scan-shift cycles.

Abstract: A scan-based method for testing delay faults in a circuit comprising controlling a subset of state inputs of the circuit by a skewed-load approach and controlling all inputs other than said subset of state inputs by a broad-side approach.

Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent of the test pattern set.