Abstract: Disclosed is an apparatus and method for testing an IC having a plurality of scan chains. A test input is transmitted over a tester channel to at least one scan chain during a time interval. Specifically, a memory element stores a first test input transmitted during a first time interval and a combinational circuit connected to the memory element and scan chain transmits to the scan chain one of a) the first test input and b) a second test input transmitted over the tester channel during a second time interval occurring after the first time interval.

Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine and a method of decompressing scan chains for testing logic circuits.

Abstract: Determining a test point location in a structured application specific integrated circuit (ASIC) includes using one or more unused cells of the structured ASIC. In particular, an unused cell of the structured ASIC is identified and then a test point is inserted at the unused cell of the structured ASIC (e.g., if the unused cell is neighboring at least one used cell of the structured ASIC).

Abstract: A test output compaction architecture and method that takes advantage of a response shaper in order to minimize masking of faults during compaction. A response shaper is inserted between a plurality of scan chains and an output compactor. The response shaper receives output responses from scan chains and reshapes the output responses in a manner that minimizes masking of faults by the output compactor.

Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

Abstract: A spatial compactor design and technique for the compaction of test response data is herein disclosed which advantageously provides a scan-out response with multiple opportunities to be observed on different output channels in one to several scan-shift cycles.

Abstract: Disclosed is a method and apparatus for improved delay fault testing by optimizing the order of scan cells in a scan chain. The order of the scan cells is determined by using a cost value for an order of scan cells, the cost value being computed from costs assigned to orderings of individual pairs of scan cells. These costs can be based on the number of faults that are untestable when the pair of scan cells are placed consecutively in the scan chain. The disclosed techniques allow for enhanced delay fault coverage by rearranging scan flip-flops without increasing routing overhead.

Abstract: A logic circuit comprising at least one input, one output and a delay fault circuit. The delay fault circuit includes a first standard scan cell, a combinational test point positioned immediately after the first standard scan cell in a scan chain and a second standard scan cell positioned immediately after the combinational test point in the scan chain.

Abstract: A test output compaction arrangement and a method of generating control patterns for unknown blocking is herein disclosed. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.

Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent of the test pattern set.

Abstract: An improved test output compaction architecture and method is disclosed that takes advantage of a response shaper in order to minimize masking of faults during compaction.

Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine and a method of decompressing scan chains for testing logic circuits.

Abstract: The present invention is directed to improved delay fault testing by optimizing the order of scan cells in a scan chain.

Abstract: Techniques for generating a test set for hard to detect faults is disclosed. A set of hard to detect faults is identified. A test set for the hard to detect faults is generated by using an improved automatic test pattern generator. The improved automatic test pattern generator is adapted to consider hardware overhead and test sequence lengths, the hardware overheads being incurred when each new testcube is added to the test set. Parallel and serial type test per scan built-in self test circuits designed and adapted to use the disclosed improved automatic test pattern generator are also disclosed.

Abstract: A scan-based method for testing delay faults in a circuit comprising controlling a subset of state inputs of the circuit by a skewed-load approach and controlling all inputs other than said subset of state inputs by a broad-side approach.

Abstract: A logic circuit comprising at least one input, one output and a delay fault circuit. The delay fault circuit includes a first standard scan cell, a combinational test point positioned immediately after the first standard scan cell in a scan chain and a second standard scan cell positioned immediately after the combinational test point in the scan chain.

Abstract: A test system for a circuit board, wherein said circuit board has a plurality of cores such that at least one of said plurality of cores is adapted to use a test protocol independent of a communication fabric used in the circuit board.

Abstract: Techniques for generating a test set for hard to detect faults is disclosed. A set of hard to detect faults is identified. A test set for the hard to detect faults is generated by using an improved automatic test pattern generator. The improved automatic test pattern generator is adapted to consider hardware overhead and test sequence lengths, the hardware overheads being incurred when each new testcube is added to the test set. Parallel and serial type test per scan built-in self test circuits designed and adapted to use the disclosed improved automatic test pattern generator are also disclosed.