Abstract: The present invention is related to an integrated circuit having an SiC etch stop layer fabricated using a method for removal of silicon carbide layers and in particular amorphous SiC of a substrate comprising the steps of: converting at least partly said exposed part of said carbide-silicon layer into an oxide-silicon layer by exposing said carbide-silicon layer to an oxygen containing plasma; and removing said oxide-silicon layer from said substrate.

Abstract: A method for forming an opening in an organic insulating layer by covering the insulating layer with a bilayer containing a resist hard mask layer and a resist layer on top of the resist hard mask layer. The bilayer is patterned, and an opening is created by plasma etching the insulating layer in a reaction chamber containing a gas mixture. The plasma etching is controlled so that virtually no etch residues are deposited and so that the side walls of the opening are fluorinated to enhance the anisotropy of the etching. The gas mixture can be a mixture of a fluorine-containing gas and an inert gas, a mixture of an oxygen-containing gas and an inert gas, or a mixture of hydrogen bromide and an additive.

Abstract: An exemplary method for depositing a layer on a surface of a dielectric layer where the dielectric layer contains an organic material comprises exposing the surface of the dielectric layer to a substance, such as a substance containing nitrogen. This exposure modifies, at least, the exposed surface of the dielectric layer. The method further includes depositing a layer, such as a barrier layer, using an atomic layer deposition process on the exposed surface of the dielectric layer. In certain embodiments, exposure of the wafer to the substance containing nitrogen result in a first region of the dielectric having a first concentration of nitrogen incorporated and a second region having a second amount of nitrogen incorporated in the dielectric layer, the second concentration being higher greater than the first concentration.

Abstract: The present invention is related to a metallization structure on a fluorine-containing dielectric. This metallization structure includes a conductive pattern; a fluorine-containing dielectric; and a barrier layer containing a material, i.e. a near noble metal such as Co, Ni, Pt, and Pd. The barrier layer includes at least a first part, being positioned between the fluorine-containing dielectric and the conductive pattern, the first part containing at least a first and a second sub-layer, the first sub-layer contacting the fluorine-containing dielectric being impermeable for fluorine.

Abstract: The present invention concerns a method to produce a porous oxygen-silicon insulating layer comprising following steps:

Abstract: A method for anisotropic plasma etching of organic-containing insulating layers is disclosed. According to this method at least one opening is created in an organic-containing insulating layer formed on a substrate. These openings are created substantially without depositing etch residues by plasma etching said insulating layer in a reaction chamber containing a gaseous mixture which is composed such that the plasma etching is highly anisotropic. Examples of such gaseous mixtures are a gaseous mixture comprising a fluorine-containing gas and an inert gas, or a gaseous mixture comprising an oxygen-containing gas and an inert gas, or a gaseous mixture comprising HBr and an additive. The plasma etching of the organic-containing insulating layer can be performed using a patterned bilayer as an etch mask, said bilayer comprising a hard mask layer, being formed on said organic-containing insulating layer, and a resist layer being formed on said hard mask layer.

Abstract: A replacement gate process is disclosed comprising the steps of forming a dummy gate stack on a substrate, depositing a PMD layer on the substrate and polishing this PMD layer to expose the top surface of the dummy gate stack. The dummy gate stack can be removed selective to the spacers and the PMD layer. SiC is used as spacer or CMP stop layer to improve the uniformity of the PMD CMP step. SiC can also be used as etch stop layer during the etching of the contact holes or during the formation of a T-gate.

Abstract: The present invention is related to an integrated circuit having an SiC etch stop layer fabricated using a method for removal of silicon carbide layers and in particular amorphous SiC of a substrate comprising the steps of: converting at least partly said exposed part of said carbide-silicon layer into an oxide-silicon layer by exposing said carbide-silicon layer to an oxygen containing plasma; and removing said oxide-silicon layer from said substrate.

Abstract: The present invention is related to a method for removal of silicon carbide layers and in particular amorphous SiC of a substrate. Initially, the exposed part of a carbide-silicon layer is at least partly converted into an oxide-silicon layer by exposing the carbide-silicon layer to an oxygen containing plasma. The oxide-silicon layer is then removed from the substrate.

Abstract: The present invention concerns a method to produce a porous oxygen-silicon insulating layer comprising following steps: applying a silicon oxygen layer to a substrate exposing the said substrate to a HF ambient.

Abstract: This invention relates to Integrated Circuit (IC) processing and fabrication. A device and a method are provided for etching an opening in an insulating layer while depositing a barrier layer on the side walls of the opening without essentially depositing a barrier layer on the bottom of the opening.

Abstract: A method for anisotropic plasma etching of organic-containing insulating layers is disclosed. According to this method at least one opening is created in an organic-containing insulating layer formed on a substrate. These openings are created substantially without depositing etch residues by plasma etching said insulating layer in a reaction chamber containing a gaseous mixture which is composed such that the plasma etching is highly anisotropic. Examples of such gaseous mixtures are a gaseous mixture comprising a fluorine-containing gas and an inert gas, or a gaseous mixture comprising an oxygen-containing gas and an inert gas, or a gaseous mixture comprising HBr and an additive. The plasma etching of the organic-containing insulating layer can be performed using a patterned bilayer as an etch mask, said bilayer comprising a hard mask layer, being formed on said organic-containing insulating layer, and a resist layer being formed on said hard mask layer.

Abstract: The present invention is related to a metallization structure on a fluorine-containing dielectric and a method for fabrication thereof. This metallization structure comprises a conductive pattern; a fluorine-containing dielectric; and a barrier layer containing a material, i.e. a near noble metal such as Co, Ni, Pt and Pd, said barrier layer comprising at least a first part, being positioned between said fluorine-containing dielectric and said conductive pattern, said first part containing at least a first and a second sub-layer, said first sub-layer contacting said fluorine-containing dielectric and being impermeable for fluorine. Particularly by depositing a layer of said material on a fluorine-containing dielectric, a stable and thin layer of a fluoride of said material is formed in a self-limiting way.

Abstract: A scaleable device concept and particularly a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. By using such shallow junctions, which are obtained using L-shaped spacers, the gate overlap is no longer dependent on the junction depth of the source/drain contact regions. Particularly the L-shaped spacers are used to locally reduce the penetration depth of the source/drain implantation in the substrate. This concept is particularly interesting for FET's having a channel length below 0.25 &mgr;m because this approach broadens the process window of the silicidation process of the source/drain contact regions. Moreover, the extension regions have to be subjected only to a limited thermal budget.

Abstract: The present invention concerns a method for stripping the photoresist layer and the crust from a semiconductor. The crust has been formed with as a result of an ion implantation step, wherein the method comprises an ion assisted plasma step using a mixture of water vapour, helium and a F-containing compound in which radicals are generated, and the step of contacting said photoresist layer and crust with said radicals to remove said photoresist layer and crust from said semiconductor surface. Said plasma step is preferably an ion assisted plasma step.

Abstract: The present invention concerns a method to produce a porous oxygen-silicon insulating layer comprising following steps:

Abstract: A replacement gate process is disclosed comprising the steps of forming a dummy gate stack on a substrate, depositing a PMD layer on the substrate and polishing this PMD layer to expose the top surface of the dummy gate stack. The dummy gate stack can be removed selective to the spacers and the PMD layer. SiC is used as spacer or CMP stop layer to improve the uniformity of the PMD CMP step. SiC can also be used as etch stop layer during the etching of the contact holes or during the formation of a T-gate.

Abstract: The present invention is related to a metallization structure on a fluorine-containing dielectric and a method for fabrication thereof. This metallization structure comprises a conductive pattern; a fluorine-containing dielectric; and a barrier layer containing a material, i.e. a near noble metal such as Co, Ni, Pt and Pd, said barrier layer comprising at least a first part, being positioned between said fluorine-containing dielectric and said conductive pattern, said first part containing at least a first and a second sub-layer, said first sub-layer contacting said fluorine-containing dielectric and being impermeable for fluorine. Particularly by depositing a layer of said material on a fluorine-containing dielectric, a stable and thin layer of a fluoride of said material is formed in a self-limiting way.

Abstract: The present invention discloses the formation of a hard mask layer in an organic polymer layer by modifying at least locally the chemical composition of a part of said exposed organic low-k polymer. This modification starts from an exposed surface of the polymer and extends into the polymer thereby increasing the chemical resistance of the modified part of the polymer. As a result, this modified part can be used as a hard mask or an etch stop layer for plasma etching.

Abstract: A scaleable device concept and particularly a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. By using such shallow junctions, which are obtained using L-shaped spacers, the gate overlap is no longer dependent on the junction depth of the source/drain contact regions. Particularly the L-shaped spacers are used to locally reduce the penetration depth of the source/drain implantation in the substrate. This concept is particularly interesting for FET's having a channel length below 0.25 &mgr;m because this approach broadens the process window of the silicidation process of the source/drain contact regions. Moreover, the extension regions have to be subjected only to a limited thermal budget.