Patents by Inventor Sergey A. Voronin

Sergey A. Voronin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818482
    Abstract: Methods are disclosed to detect plasma light emissions during plasma processing, to analyze light intensity data associated with the plasma source, and to adjust operating parameters for the plasma source and/or the process chamber based upon light intensity distributions associated with the plasma processing. The light intensity distributions for the plasma sources and related analysis can be conducted across multiple processing tools. For some embodiments, plasma discharge stability and/or chamber-to-chamber matching information is determined based upon light intensity data, and the operation of the processing tools are adjusted or controlled based upon stability and/or matching determinations. The disclosed embodiments thereby provide simple, low-cost solutions to assess and improve plasma sources and discharge stability for plasma processing tools such as plasma etch and deposition tools.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: October 27, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Yoshida, Jason Marion, Sergey Voronin, Alok Ranjan
  • Patent number: 10818502
    Abstract: Systems and methods are disclosed for plasma discharge ignition to reduce surface particles and thereby decrease defects introduced during plasma processing. A microelectronic workpiece is positioned on a holder within a process chamber that includes a first radio frequency (RF) power source configured to couple RF power to a top portion of the process chamber, a second RF power source configured to couple RF power to the holder, and a direct current (DC) power supply. Initially, a process gas for plasma process is flowed into the process chamber. The process gas is ignited to form plasma by activating the second RF power source to apply RF power to the holder. Subsequently, the microelectronic workpiece is clamped to the holder by applying the positive voltage to the holder with the DC power supply, and the first RF power source is activated to maintain the plasma within the process chamber.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 27, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sergey Voronin, Jason Marion, Yusuke Yoshida, Alok Ranjan, Takashi Enomoto, Yoshio Ishikawa
  • Patent number: 10811269
    Abstract: Sidewall etching of substrate features may be achieved by employing an etch stop layer formed over the features. The etch stop layer is thinner on sidewalls of the features as compared to the bottom of the features. The lateral etching of the features is achieved by use of an over etch which breaks through the etch stop layer on the sidewalls of the features but does not break through the etch stop layer formed at the bottom of the features. The use of the etch stop layer allows for lateral etching while preventing unwanted vertical etching. The lateral etching may be desirable for use in a number of structures, including but not limited to 3D structures. The lateral etching may also be used to provide vertical sidewalls by reducing the sidewall taper angle.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: October 20, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shyam Sridhar, Nayoung Bae, Sergey Voronin, Alok Ranjan
  • Patent number: 10811273
    Abstract: Provided is a method of modifying a surface of a substrate for improved etch selectivity of nitride etching. In an embodiment, the method includes providing a substrate with a nitride-containing structure, the nitride-containing structure having an oxygen-nitrogen layer. The method may also include performing a surface modification process on the nitride-containing structure with the oxygen-nitrogen layer using one or more gases, the surface modification process generating a cleaned nitride-containing structure. Additionally, the method may include performing a nitride etch process using the cleaned nitride-containing structure, wherein the etched nitride-containing structure are included in 5 nm or lower technology nodes, and the nitride etch process meets target etch rate and target etch selectivity, and the cleaned nitride-containing structure meet target residue cleaning objectives.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 20, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Christopher Talone, Erdinc Karakas, Andrew Nolan, Sergey A. Voronin, Alok Ranjan
  • Patent number: 10777385
    Abstract: Embodiments of systems and methods for RF power distribution in a multi-zone electrode array are described. A system may include a plasma source configured to generate a plasma field. Also, the system may include an RF power source coupled to the plasma source and configured to supply RF power to the plasma source. The system may also include a source controller coupled to the RF power source and configured to control modulation of the RF power supplied to the plasma source to enhance uniformity of a plasma field generated by the plasma source.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 15, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Sergey Voronin, Alok Ranjan
  • Publication number: 20200273992
    Abstract: Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 27, 2020
    Inventors: Sergey Voronin, Christopher Catano, Sang Cheol Han, Shyam Sridhar, Yusuke Yoshida, Christopher Talone, Alok Ranjan
  • Publication number: 20200273711
    Abstract: In one example, a method of processing a substrate includes receiving a substrate in a processing chamber, the substrate having an etch mask positioned over an underlying layer to be etched, where the underlying layer is a silicon-containing layer. The method includes executing a first etch process that includes forming a first plasma from a first process gas that includes hydrogen bromide or chlorine and etching the underlying layer using products of the first plasma. The method includes executing a second etch process that includes forming a second plasma from a second process gas that includes fluorine and etching the substrate using products from the second plasma. The method may include alternating between the first etch process and the second etch process.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 27, 2020
    Inventors: Yusuke Yoshida, Sergey Voronin, Shyam Sridhar, Caitlin Philippi, Christopher Talone, Alok Ranjan
  • Publication number: 20200266070
    Abstract: A method of etching a substrate includes generating plasma comprising a first concentration of an etchant and a second concentration of an inhibitor and etching the substrate by exposing an exposed interface between a first material and a second material to the plasma. The first material includes a lower reactivity to both the etchant and the inhibitor than the second material. The first concentration is less than the second concentration. Etching the substrate includes etching the first material and the second material at the exposed interface to form an etched indentation including an enriched region of the second material, forming a passivation layer at the enriched region using the inhibitor, and etching the first material at the etched indentation. The passivation layer reduces an etch rate of the second material to a reduced rate that is less than an etch rate of the first material.
    Type: Application
    Filed: February 20, 2020
    Publication date: August 20, 2020
    Inventors: Sergey Voronin, Christopher Catano, Nicholas Joy, Alok Ranjan, Christopher Talone
  • Patent number: 10651017
    Abstract: Provided are methods and systems for operation instability detection in a surface wave plasma source. In an embodiment a system for plasma processing may include a surface wave plasma source configured to generate a plasma field. The system may also include an optical sensor configured to generate information characteristic of optical energy collected in a region proximate to the surface wave plasma source. Additionally, the system may include a sensor logic unit configured to detect a region of instability proximate to the surface wave plasma source in response to the information generated by the optical sensor.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: May 12, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sergey Voronin, Jason Marion, Alok Ranjan
  • Publication number: 20200105510
    Abstract: Methods are disclosed to detect plasma light emissions during plasma processing, to analyze light intensity data associated with the plasma source, and to adjust operating parameters for the plasma source and/or the process chamber based upon light intensity distributions associated with the plasma processing. The light intensity distributions for the plasma sources and related analysis can be conducted across multiple processing tools. For some embodiments, plasma discharge stability and/or chamber-to-chamber matching information is determined based upon light intensity data, and the operation of the processing tools are adjusted or controlled based upon stability and/or matching determinations. The disclosed embodiments thereby provide simple, low-cost solutions to assess and improve plasma sources and discharge stability for plasma processing tools such as plasma etch and deposition tools.
    Type: Application
    Filed: September 19, 2019
    Publication date: April 2, 2020
    Inventors: Yusuke Yoshida, Jason Marion, Sergey Voronin, Alok Ranjan
  • Publication number: 20200027736
    Abstract: Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 23, 2020
    Inventors: Yusuke Yoshida, Christopher Catano, Christopher Talone, Nicholas Joy, Sergey Voronin
  • Patent number: 10529540
    Abstract: Methods and systems for treating a substrate are described. In an embodiment, a method may include receiving a microelectronic substrate in a plasma processing chamber. A method may also include receiving process gas in the plasma processing chamber. Additionally, a method may include applying energy to the process gas with a first energy source and applying energy to the process gas with a second energy source. The method may further include selectively adjusting at least one of the first energy source and the second energy source between a first state and a second state.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: January 7, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Sergey Voronin, Christopher Talone, Alok Ranjan
  • Publication number: 20190318913
    Abstract: Multiple harmonic frequency components are used for plasma excitation in a plasma process. Relative amplitude and/or phase shift between the different frequency components is controlled so as to provide desired ion energy plasma properties. The relative amplitude and/or phase shift may be controlled without direct and/or manual ion energy measurements. Rather, the ion energy within the plasma may be dynamically controlled by monitoring one or more electrical characteristics within the plasma apparatus, such as for example, impedance levels, electrical signals in the radio frequency (RF) generator, electrical signals in a the matching networks, and electrical signals in other circuits of the plasma processing apparatus. The monitoring and control of the ion energy may be accomplished dynamically during the plasma process so as to maintain a desired ion energy distribution.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 17, 2019
    Inventors: Yusuke Yoshida, Sergey Voronin, Alok Ranjan, David J. Coumou, Scott E. White
  • Publication number: 20190318916
    Abstract: Plasma ion energy distribution for ions having different masses is controlled by controlling the relationship between a base RF frequency and a harmonic RF frequency. By the controlling the RF power frequencies, characteristics of the plasma process may be changed based on ion mass. The ions that dominate etching may be selectively based upon whether an ion is lighter or heavier than other ions. Similarly, atomic layer etch processes may be controlled such that the process may be switched between a layer modification step and a layer etch step though adjustment of the RF frequencies. Such switching is capable of being performed within the same gas phase of the plasma process. The control of the RF power includes controlling the phase difference and/or amplitude ratios between a base RF frequency and a harmonic frequency based upon the detection of one or more electrical characteristics within the plasma apparatus.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 17, 2019
    Inventors: Yusuke Yoshida, Sergey Voronin, Alok Ranjan, David J. Coumou, Scott E. White
  • Publication number: 20190304750
    Abstract: Methods and systems for treating a substrate are described. In an embodiment, a method may include receiving a microelectronic substrate in a plasma processing chamber. A method may also include receiving process gas in the plasma processing chamber. Additionally, a method may include applying energy to the process gas with a first energy source and applying energy to the process gas with a second energy source. The method may further include selectively adjusting at least one of the first energy source and the second energy source between a first state and a second state.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Sergey Voronin, Christopher Talone, Alok Ranjan
  • Publication number: 20190259623
    Abstract: Sidewall etching of substrate features may be achieved by employing an etch stop layer formed over the features. The etch stop layer is thinner on sidewalls of the features as compared to the bottom of the features. The lateral etching of the features is achieved by use of an over etch which breaks through the etch stop layer on the sidewalls of the features but does not break through the etch stop layer formed at the bottom of the features. The use of the etch stop layer allows for lateral etching while preventing unwanted vertical etching. The lateral etching may be desirable for use in a number of structures, including but not limited to 3D structures. The lateral etching may also be used to provide vertical sidewalls by reducing the sidewall taper angle.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 22, 2019
    Inventors: Shyam Sridhar, Nayoung Bae, Sergey Voronin, Alok Ranjan
  • Patent number: 10237916
    Abstract: This disclosure relates to a temperature control system that may be used in a plasma processing system that treats microelectronic substrates using plasma. The temperature control system may include a heating array disposed adjacent to the microelectronic substrate and that may selectively generate heat at different portions of the microelectronic substrate. The heating array may include heating modules that selectively generate heat depending upon a breakover voltage of a Silicon Diode for Alternating Current (SIDAC). The amount of heat generated heat may depend upon the resistance of the heating module and the duty cycle of the variable voltage signal.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: March 19, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Sergey A. Voronin, Alok Ranjan
  • Publication number: 20190080926
    Abstract: Provided is a method of modifying a surface of a substrate for improved etch selectivity of nitride etching. In an embodiment, the method includes providing a substrate with a nitride-containing structure, the nitride-containing structure having an oxygen-nitrogen layer. The method may also include performing a surface modification process on the nitride-containing structure with the oxygen-nitrogen layer using one or more gases, the surface modification process generating a cleaned nitride-containing structure. Additionally, the method may include performing a nitride etch process using the cleaned nitride-containing structure, wherein the etched nitride-containing structure are included in 5 nm or lower technology nodes, and the nitride etch process meets target etch rate and target etch selectivity, and the cleaned nitride-containing structure meet target residue cleaning objectives.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 14, 2019
    Inventors: Christopher Talone, Erdinc Karakas, Andrew Nolan, Sergey A. Voronin, Alok Ranjan
  • Patent number: 10204832
    Abstract: Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate in a processing chamber, the substrate having a plurality of structures and a pattern, the substrate including an underlying layer and a target layer, at least one structure intersecting with another structure, each intersection having an intersection angle and a corner, the integration scheme requiring a vertical corner profile at each intersection; alternatingly and sequentially etching and cleaning the substrate to transfer the pattern onto the target layer and to achieve a target vertical corner profile at each intersection; controlling selected two or more operating variables of the integration scheme in the alternating and sequential etching and cleaning operations in order to achieve target integration objectives.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: February 12, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Sergey A. Voronin, Christopher Talone, Alok Ranjan
  • Publication number: 20180323045
    Abstract: Manufacturing methods are disclosed to reduce surface particle impurities after a plasma process (e.g., etch, deposition, etc.) by repelling particles trapped within particle wells to reduce surface particle impurities on microelectronic workpieces after termination of the plasma process. Rather than turn off pressure and source power at the termination of the plasma process, the disclosed embodiments first enter a sequence to adjust process parameters to repel particles in a particle well in order to reduce or eliminate the particle well prior to terminating the plasma process. During this particle repel sequence, certain disclosed embodiments adjust parameters to maintain an electrostatic field above the surface of the wafer utilizing low plasma density and ion energy conditions that help to repel particles from the microelectronic workpiece. The disclosed methods allow for the particle well to be exhausted well prior to the collapse of electrostatic forces when the plasma process is terminated.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 8, 2018
    Inventors: Jason Marion, Yusuke Yoshida, Brendan Bathrick, Sergey Voronin, Alok Ranjan